cxd2589q Sony Electronics, cxd2589q Datasheet - Page 25

• Manufacturer Part Number: cxd2589q
• Description: Cd Digital Signal Processor
• Manufacturer: Sony Electronics

Peak meter
Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively,
results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data
values (absolute value, upper 8bits) for the left and right channels can be read from SQSO by inputting 16
clocks to SQCK. Peak detection is not performed during SQCK input, and the peak register does not change
during readout. This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant
of 270µs to 400µs. The time during which SQCK input is high should be 270µs or less. Also, peak detection is
restarted 270µs to 400µs after SQCK input.
The peak register is reset with each readout (16 clocks input to SQCK).
The maximum value in peak detection mode is detected and held in this status until the next readout. When
switching to peak detection mode, readout should be performed one time initially to reset the peak detection
register.
Peak detection can also be performed for previous value hold and average value interpolation data.
Traverse monitor count value setting
These bits are set when monitoring the traverse condition of the SENS output according to the CNIN frequency
division.
Monitor output switching
The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B.
Command bit
SQCK
SQSO
XLAT
TRM1
(Peak meter)
Command bit
0
0
1
1
MTSL1
0
0
1
TRM0
0
1
0
1
1/64 frequency division
1/128 frequency division
1/256 frequency division
1/512 frequency division
MTSL0
L0
0
1
0
Processing
Pin No.
L1
L2
L3
XUGF
MNT1
RFCK
47
L4
L5
L6
– 25 –
XPCK
MNT0
XPCK
Mode description
L7
48
R0
R1
XROF
R2
MNT3
GFS
49
R3
R4
R5
GTOP
C2PO
C2PO
50
R6
R7
CXD2589Q