cxd2589q Sony Electronics, cxd2589q Datasheet - Page 24

• Manufacturer Part Number: cxd2589q
• Description: Cd Digital Signal Processor
• Manufacturer: Sony Electronics

PER0 to 7
SPOA, B
L0 to L7,
R0 to R7
VF0 to 7
C1F1
ALOCK
XRAOF
EMPH
WFCK
SCOR
Signal
GTOP
LOCK
RFCK
FOK
GFS
0
1
1
Command bit
CPUSR = 1
CPUSR = 0
C1F2
RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.
Focus OK
High when the frame sync and the insertion protection timing match.
GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight
consecutive samples, a low signal is output.
High when the playback disc has emphasis.
GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is
output. If GFS is low eight consecutive samples, a low signal is output.
Used in CAV-W mode. Results of measuring the disc rotational velocity. (See Timing Chart 2-3.)
VF0 = LSB, VF7 = MSB.
SPOA and B pin inputs.
Write frame clock output.
High when either subcode sync S0 or S1 is detected.
High when the sync protection window is open.
Read frame clock output.
Low when the built-in 16K RAM exceeds the ±4 frame jitter margin.
Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak
data. L0 and R0 are LSB.
0
0
1
No Error
Single Error Correction
Irretrievable Error
C1 correction status
XLON pin is high.
XLON pin is low.
– 24 –
Description
Processing
C2F1
0
1
1
C2F2
0
0
1
No Error
Single Error Correction
Irretrievable Error
C2 correction status
CXD2589Q