ATSAM3S ATMEL [ATMEL Corporation], ATSAM3S Datasheet - Page 50

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ATSAM3S

Manufacturer Part Number
ATSAM3S
Description
AT91 ARM Cortex M3-based Processor
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet

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12.7
50
Pulse Width Modulation Controller (PWM)
SAM3S Summary
• Each channel is user-configurable and contains:
• Two global registers that act on all three TC Channels
• Quadrature decoder
• 2-bit Gray Up/Down Counter for Stepper Motor
• One Four-channel 16-bit PWM Controller, 16-bit counter per channel
• Common clock generator, providing Thirteen Different Clocks
• Independent channel programming
• Synchronous Channel mode
• Connection to one PDC channel
• independent event lines which can send up to 4 triggers on ADC within a period
– Interval Measurement
– Pulse Generation
– Delay Timing
– Pulse Width Modulation
– Up/down Capabilities
– Three external clock inputs
– Five internal clock inputs
– Two multi-purpose input/output signals
– Advanced line filtering
– Position / revolution / speed
– A Modulo n counter providing eleven clocks
– Two independent Linear Dividers working on modulo n counter outputs
– High Frequency Asynchronous clocking mode
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Programmable selection of the output waveform polarity
– Programmable center or left aligned output waveform
– Independent Output Override for each channel
– Independent complementary Outputs with 12-bit dead time generator for each
– Independent Enable Disable Commands
– Independent Clock Selection
– Independent Period and Duty Cycle, with Double Buffering
– Synchronous Channels share the same counter
– Mode to update the synchronous channels registers after a programmable number
– Offers Buffer transfer without Processor Intervention, to update duty cycle of
channel
of periods
synchronous channels
6500AS–ATARM–11-Dec-09

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