ATSAM3S ATMEL [ATMEL Corporation], ATSAM3S Datasheet - Page 27

• Manufacturer Part Number: ATSAM3S
• Description: AT91 ARM Cortex M3-based Processor
• Manufacturer: ATMEL [ATMEL Corporation]

7. Processor and Architecture
7.1
7.2
7.3
7.4
6500AS–ATARM–11-Dec-09
ARM Cortex-M3 Processor
APB/AHB bridge
Matrix Masters
Matrix Slaves
The SAM3S product embeds one peripheral bridge:
The peripherals of the bridge are clocked by MCK.
The Bus Matrix of the SAM3S product manages 4 masters, which means that each master can
perform an access concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to sim-
plify the addressing, all the masters have the same decodings.
Table 7-1.
The Bus Matrix of the SAM3S product manages 5 slaves. Each slave has its own arbiter, allow-
ing a different arbitration per slave.
Table 7-2.
Master 0
Master 1
Master 2
Master 3
Slave 0
Slave 1
Slave 2
Slave 3
Slave 4
• Version 2.0
• Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit
• Harvard processor architecture enabling simultaneous instruction fetch with data load/store
• Three-stage pipeline
• Single cycle 32-bit multiply
• Hardware divide
• Thumb and Debug states
• Handler and Thread modes
• Low latency ISR entry and exit
List of Bus Matrix Masters
List of Bus Matrix Slaves
Internal SRAM
Internal ROM
Internal Flash
External Bus Interface
Peripheral Bridge
Cortex-M3 Instruction/Data
Cortex-M3 System
Peripheral DMA Controller (PDC)
CRC Calculation Unit
SAM3S Summary
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