em78f644nso28s ELAN Microelectronics Corp, em78f644nso28s Datasheet - Page 34

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em78f644nso28s

Manufacturer Part Number
em78f644nso28s
Description
Flash Series 8-bit Microcontroller
Manufacturer
ELAN Microelectronics Corp
Datasheet
EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
24 •
In Capture mode, the pulse width, period and duty of the TC1 input pin are
measured under this mode to decode the remote control signal. The counter is set as
free running by the internal clock. On a rising (falling) edge of TC1 pin input, the
contents of the counter is loaded into TCR1DA, then the counter is cleared and
interrupt is generated. On a falling (rising) edge of the TC1 pin input, the contents of
the counter are loaded into TCR1DB. At the next rising edge of the TC1 pin input
while the counter is still counting, the contents of the counter are loaded into
TCR1DA. Then, the counter is cleared and interrupt is generated again. If an
overflow occurs before an edge is detected, the FFH is loaded into TCR1DA and the
overflow interrupt is generated. During interrupt processing, you can determine
whether an overflow has occurred by checking the TCR1DA value is FFH. After an
interrupt (capture to TCR1DA or overflow detection) is generated, capture and
overflow detection are halted until TCR1DA is read out.
6.1.19 Bank 1 R6 TCR1DA (Timer 1 Data Buffer A)
Bit 7 ~ Bit 0 (TCR1DA7 ~ TCR1DA0): Data buffer of 8-bit Timer/Counter 1.
6.1.20 Bank 1 R7 TCR1DB (Timer 1 Data Buffer B)
Bit 7 ~ Bit 0 (TCR1DB7 ~ TCR1DB0): Data buffer of 8-bit Timer/Counter 1.
TCR1DA7 TCR1DA6 TCR1DA5 TCR1DA4 TCR1DA3 TCR1DA2 TCR1DA1 TCR1DA0
TCR1DB7 TCR1DB6 TCR1DB5 TCR1DB4 TCR1DB3 TCR1DB2 TCR1DB1 TCR1DB0
Reading TCR1DA
Capture Mode Timing
Bit 7
Bit 7
TC1 pin input
Clock source
TC1 interrupt
Up-counter
TCR1DA
TCR1DB
Bit 6
Bit 6
K-2
Figure 6-3b Capture Mode Timing Diagram
K-1 K 0
Bit 5
For F641/541N, this register is reserved.
Bit 5
For F641/541N, this register is reserved.
K
capture
1
Bit 4
Bit 4
m-1 m m+1
(This specification is subject to change without further notice)
NOTE
NOTE
m
Bit 3
Bit 3
Product Specification (V1.0) 05.05.2010
n-1 n 0
n
capture
1
Bit 2
Bit 2
2
3
Bit 1
Bit 1
FE FF0
FE
FF (overflow)
overflow
1
Bit 0
Bit 0
2
3

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