em78f644nso28s ELAN Microelectronics Corp, em78f644nso28s Datasheet - Page 128

• Manufacturer Part Number: em78f644nso28s
• Description: Flash Series 8-bit Microcontroller
• Manufacturer: ELAN Microelectronics Corp

EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
118 •
The Sleep (power down) mode is asserted by executing the “SLEP” instruction.
While entering Sleep mode, the WDT (if enabled) is cleared but keeps on running
until wake-up is triggered by one of the following events (wake-up time in RC mode,
the wake-up time is 10µs and in High Crystal (XTAL) mode is 800µs):
Event 1) External reset input on /RESET pin
Event 2) WDT time-out (if enabled)
Event 3) Port 6 input status changes (if enabled)
Event 4) Comparator output status changes (if CMPWE is enabled)
Event 5) External (P60, /INT) pin changes (if EXWE is enabled)
Event 6) SPI receives data while SPI is acting as Slave device (if SPIWE is enabled)
The first two events will cause the IC to reset. The T and P flags of R3 can be used
to determine the source of the reset (wake-up). Events 3, 4, 5, & 6 are considered as
continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) determines whether or not the controller branches to the interrupt vector
following a wake-up. If ENI is executed before SLEP, the instruction will begin to
execute from the Address 0×6, 0×15, 0×3, 0×12 after wake-up. If DISI is executed
before SLEP, the execution will restart from the instruction right next to SLEP after
wake-up. In RC mode, the wake-up time is 10µs and that of High Crystal (XTAL)
mode, is 800µs.
Only one event of Events 2 to 6 can be enabled before entering into Sleep mode.
That is-
a) If WDT is enabled before SLEP, all the RA register bits are disabled. Hence, the
b) If Port 6 Input Status Change is used to wake-up the IC and the ICWE bit of RA
The bits of IOCB register are set to all "1".
The bits of IOCC register are set to all "0".
The bits of IOCD register are set to all "1".
The bits of IOCE register are set to all "0".
The bits of IOCF register are set to all "0".
IC can wake-up only under Events 1 or 2 conditions. Refer to the Interrupt
section (Section 6.12) for further details.
register is enabled before SLEP, WDT must be disabled. Hence, the IC can
wake-up only under Event 3 conditon.
(This specification is subject to change without further notice)
Product Specification (V1.0) 05.05.2010