em78f644nso28s ELAN Microelectronics Corp, em78f644nso28s Datasheet - Page 104

• Manufacturer Part Number: em78f644nso28s
• Description: Flash Series 8-bit Microcontroller
• Manufacturer: ELAN Microelectronics Corp

EM78F648/644/642/641/548/544/542/541N
8-Bit Microcontroller
94 •
6.3.107 Bank1 R3A: (Not Used)
6.3.108 Bank1 R3B: PRDxL (PWM A/B/C Period Buffer Low Bits
6.3.109 Bank1 R3C: DTxL (PWM1/2 Duty Buffer Low Bits
6.3.110 Bank1 R3D~R4F (Not Used)
6.3.111 Bank0 R50~R7F, Bank0~1 R80~RFF
Bits 7~4:
Bits 3~2 (PRDB[1]~PRDB[0]): PWM B period buffer low bits
Bits 1~0 (PRDA[1]~PRDA[0]): PWM A period buffer low bits
Bits 7~4:
Bits 3~2 (DTB[1]~DTB[0]):
Bits 1~0 (DTA[1]~DTA[0]):
These are all 8-bit general-purpose registers.
6.4 TCC/WDT and Prescaler
Two 8-bit counters are available as prescalers for the TCC and WDT respectively.
The PST0~PST2 bits of the TCCCR register (Bank0 R13) are used to determine the
ratio of the prescaler of TCC. Likewise, the PSW0~PSW2 bits of the WDTCR register
Bank0 R11) are used to determine the prescaler of WDT. The prescaler counter is
cleared by the instructions each time they are written into TCC. The WDT and
prescaler are cleared by the “WDTC” and “SLEP” instructions. Figure 6-11 below
depicts the circuit diagram of the TCC/WDT.
TCCDATA (Bank0 R14) is an 8-bit timer/counter. The clock source of TCC can be
internal clock or external signal input (edge selectable from the TCC pin). If the TCC
signal source is from internal clock, TCC will increase by 1 at every instruction cycle
(without prescaler). As illustrated in the following figure, if TCC signal source is from
external clock input, TCC will increase by 1 at every falling edge or rising edge of the
TCC pin. The TCC pin input time length (keep in High or low level) must be greater
than 1CLK. The TCC will stop running when sleep mode occurs.
Bit 7
Bit 7
0
0
Bit 6
Bit 6
0
0
Bit 5
Bit 5
0
0
Not used, fixed to “0” all the time.
Not used, fixed to “0” all the time.
PWM B duty buffer high bits
PWM A duty buffer high bits
Bit 4
Bit 4
Register)
0
0
(This specification is subject to change without further notice)
Register)
PRDB[1]
DTB[1]
Bit 3
Bit 3
Product Specification (V1.0) 05.05.2010
PRDB[0]
DTB[0]
Bit 2
Bit 2
PRDA[1]
DTA[1]
Bit 1
Bit 1
PRDA[0]
DTA[0]
Bit 0
Bit 0