sm8211m Nippon Precision Circuits Inc, (NPC), sm8211m Datasheet - Page 6

• Manufacturer Part Number: sm8211m
• Description: Pocsag Decoder For Pagers
• Manufacturer: Nippon Precision Circuits Inc, (NPC)

Code words (address and message signals)
Each code word comprises 32 bits as shown in table 2.
Table 2. Code word format
1. The MSB is the address/message code word control bit. It is 0 for an address signal, and 1 for a message signal.
2. Bits 2 to 21 contain the address or message information.
3. Bits 22 to 31 are BCH(31,21) format generated check bits, where BCH(n,k) = BCH(word length, number of information bits).
4. The LSB is an even-parity bit for bits 1 to 31.
Call number to call sign conversion
This conversion expands a 7-digit decimal call num-
ber into a 21-bit binary call sign, as shown in figure
2.
After expansion, the high-order 18 bits are assigned
to bits 2 to 19 (address signal), and the low-order 3
Address signal
Message signal
21-bit binary
conversion
Call sign
Code word
Flag:
0 = address signal
1 = message signal
MSB
1
7-digit decimal call
signal (gap code)
1
2
1 (MSB)
3
0
1
4
Bits 2 to 19 (18 bits)
1
1
5
Address bits
Message bits
Figure 2. Call number to call sign conversion
2 to 19
6
2
7
2
3
8
Function bits
9
20
0
0
1
1
4
SM8211M
10
Function bits
11
20
21
0
1
0
1
bits are the user-defined frame identification pattern,
which is stored in ID-ROM. The two function bits
define which of four call functions is active.
5
Bit number
12
21
20, 21
13
6
2
Function
A call
B call
C call
D call
14
BCH(31,21) generated check bits
7
15
Bits 22 to 31 (10 bits)
16
NIPPON PRECISION CIRCUITS—6
17
Check bits
Check bits
22 to 31
18
19
identificaton
3
Frame
pattern
20
Even-parity bit
Even-parity bit
32 (LSB)
21
32
LSB
(for bits 1 to 31)
Even-parity bit
4