sm8211m Nippon Precision Circuits Inc, (NPC), sm8211m Datasheet - Page 16

• Manufacturer Part Number: sm8211m
• Description: Pocsag Decoder For Pagers
• Manufacturer: Nippon Precision Circuits Inc, (NPC)

CPU Interface
SYN-VAL
If a sync code is detected with two bit errors or less
during sync code detection timing while in preamble,
lock or idle mode, SYN-VAL goes HIGH for the
duration of the next batch (544 bits long).
ADD-DET
If frame data is received and recognized with two bit
errors or less while in lock mode, ADD-DET goes
HIGH for the duration of the next code word period.
If an address is detected in the second code word in
the frame, ADD-DET stays HIGH for the duration of
two code word periods.
When an address is detected, the next 32-bit data
code word is received. The BCH(31,21) format error
check bits are checked and if a 1-bit or two consecu-
tive bit errors occur, they are corrected. Two random
bit errors, or three or more bit errors are not cor-
rected. If the corrected data MSB is 1, the data is rec-
Table 15. Error count flags
Received message codeword
E0
Internal bit
RX-DATA
0
1
0
1
RX-CLK
clock
27 28 29 30 31
E1
0
0
1
1
No errors
1-bit error
Two consecutive bit errors
Two random, or three or more
bit errors
0
1
2
Error count
Figure 9. Received message transmit timing
3
4
5
6
7
20-bit error-corrected message data
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SM8211M
ognized as a message, data reception continues and
the corrected message data and error check flags are
sent to the CPU. If the MSB is 0, the data is recog-
nized as an address signal or idle code and data
reception or data transmission to the CPU is halted.
Table 16. Parity check flag
1. The even-parity check is performed on the data before error correction.
BREAK
On a rising edge of BREAK, message reception and
received message transmission are halted. After a
BREAK interrupt, the device waits for frame address
detection or sync code detection timing. This func-
tion is useful in cases of continuing message recep-
tion, because without sync code or other detection
taking place the received data would be deemed to
have many errors.
1 codeword
PE
0
1
E0
NIPPON PRECISION CIRCUITS—16
E1
PE
Even-parity check result
An error occurred
No errors
0
1
1