sm8211m Nippon Precision Circuits Inc, (NPC), sm8211m Datasheet - Page 12

• Manufacturer Part Number: sm8211m
• Description: Pocsag Decoder For Pagers
• Manufacturer: Nippon Precision Circuits Inc, (NPC)

Address/Flag Data Transmission (CPU to SM8211M)
After device reset initialization, the address and flag
data is transmitted from the CPU on TX-DATA in
225 cycles in sync with the falling edge of TX-CLK.
(See the description in “Switch-ON mode”).
The SM8211M supports six independent addresses
(identified as A, B, C, D, E and F). Using these, it is
possible to cover all kinds of group calls.
The address data for each of the six addresses com-
prises an 18-bit address plus two function bits used
to select one of four sub-addresses. Then, one MSB
bit (0 for address signals), ten BCH(31,21) format
generated check bits and an even-parity bit are added
Table 4. Address/flag transmit format
clock
TX
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
1
2
3
4
5
6
7
8
9
Data
LBO
BS2
RF5
RF4
RF3
RF2
RF1
RF0
FF2
FF1
FF0
PL5
PL4
PL3
PL2
PL1
PL0
FL2
INV
SS
bit
S1
S0
0
0
0
0
clock
TX
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
AA17
AA16
AA15
AA14
AA13
AA12
AA11
AA10
Data
ER2
ER1
ER0
AA9
AA8
AA7
AA6
AA5
AA4
AA3
AA2
AA1
AA0
FL1
FL0
bit
0
0
0
clock
TX
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
AB17
AB16
AB15
AB14
AB13
AB12
AB11
AB10
Data
AB9
AB8
AB7
AB6
AB5
AB4
bit
0
0
0
0
0
0
0
0
0
0
0
0
clock
100 AC14 126
101 AC13 127
102 AC12 128
103 AC11 129 AD17 155
104 AC10 130 AD16 156
TX
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
AC17 123
AC16 124
AC15 125
Data
AB3
AB2
AB1
AB0
bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
clock
SM8211M
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
TX
Data
AC9
AC8
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
bit
to form 32-bit code words representing the address
information which is then stored in RAM. This
address information is then compared with the
received data to determine correct addressing.
If the number of addresses used is less than six, the
same address should be repeated as many times as
necessary to cancel the remaining addresses. Also,
each 18-bit address should be input MSB first.
The TX-CLK cycle and corresponding address data
bits are shown in table 4, and the function of each
flag is shown in tables 5 to 13.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
clock
131 AD15 157
132 AD14 158
133 AD13 159
134 AD12 160
135 AD11 161 AE17 187
136 AD10 162 AE16 188
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
TX
Data
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
bit
0
0
0
0
0
0
0
0
0
0
clock
163 AE15 189
164 AE14 190
165 AE13 191
166 AE12 192
167 AE11 193 AF17 219
168 AE10 194 AF16 220
169
170
171
172
173
174
175
176
177
178
179
180
181
182
TX
NIPPON PRECISION CIRCUITS—12
Data
AE9
AE8
AE7
AE6
AE5
AE4
AE3
AE2
AE1
AE0
bit
0
0
0
0
0
0
0
0
clock
183
184
185
186
195 AF15 221
196 AF14 222
197 AF13 223
198 AF12 224
199 AF11 225
200 AF10
201
202
203
204
205
206
207
208
TX
Data
AF9
AF8
AF7
AF6
AF5
AF4
AF3
AF2
bit
0
0
0
0
0
0
0
0
0
0
clock
209
210
211
212
213
214
215
216
217
218
TX
Data
AF1
AF0
bit
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0