as29lv016brg-90/xt Austin Semiconductor, Inc., as29lv016brg-90/xt Datasheet - Page 8

• Manufacturer Part Number: as29lv016brg-90/xt
• Description: 16 Megabit 2m X 8-bit / 1m X 16-bit Cmos 3.0 Volt-only Boot Sector Flash Memory
• Manufacturer: Austin Semiconductor, Inc.

STANDBY MODE
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs
are placed in the high impedance state, independent of
the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
(Note that this is a more restricted voltage range than
V
V
the standby current will be greater. The device requires
standard access time (t
is in either of these standby modes, before it is ready to
read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
I
shown in the table in DC Characteristics on page 27.
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t
automatic sleep mode is independent of the CE#, WE#,
and OE# control signals. Standard address access timings
provide new data when addresses are changed. While in
sleep mode, output data is latched and always available
to the system. I
represents the automatic sleep mode current specification.
AS29LV016
Rev. 2.0 06/06
CC3
IH
CC
.) If CE# and RESET# are held at V
and I
± 0.3 V, the device will be in the standby mode, but
CC4
represents the standby current specification
CC4
in the DC Characteristics on page 27
CE
) for read access when the device
Austin Semiconductor, Inc.
ACC
IH
, but not within
+ 30 ns. The
CC
± 0.3 V.
8
RESET#: HARDWARE RESET PIN
The RESET# pin provides a hardware method of resetting
the device to reading array data. When the system drives
the RESET# pin to V
device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET# pulse.
The device also resets the internal state machine to
reading array data. The operation that was interrupted
should be reinitiated once the device is ready to accept
another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse.
When RESET# is held at V
CMOS standby current (I
not within V
The RESET# pin may be tied to the system reset circuitry.
A system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from
the Flash memory.
If RESET# is asserted during a program or erase
operation, the RY/BY# pin remains a 0 (busy) until the
internal reset operation is complete, which requires a time
of t
thus monitor RY/BY# to determine whether the reset
operation is complete. If RESET# is asserted when a
program or erase operation is not executing (RY/BY# pin
is 1), the reset operation is completed within a time of
t
read data t
the tables in AC Characteristics on page 29 for RESET#
parameters and to Figure 13, on page 30 for the timing
diagram.
READY
READY
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
(not during Embedded Algorithms). The system can
(during Embedded Algorithms). The system can
BOO
BOOT SECT
BOO
BOO
BOO
RH
SS
after the RESET# pin returns to V
±0.3 V, the standby current will be greater.
T SECT
T SECTOR FLASH
T SECT
T SECT
IL
for at least a period of t
CC4
). If RESET# is held at V
SS
±0.3 V, the device draws
CO
COTS PEM
CO
CO
CO
OR FLASH
OR FLASH
OR FLASH
OR FLASH
AS29LV016
TS PEM
TS PEM
TS PEM
TS PEM
IH
.Refer to
RP
, the
IL
but