as29lv016brg-90/xt Austin Semiconductor, Inc., as29lv016brg-90/xt Datasheet - Page 16

• Manufacturer Part Number: as29lv016brg-90/xt
• Description: 16 Megabit 2m X 8-bit / 1m X 16-bit Cmos 3.0 Volt-only Boot Sector Flash Memory
• Manufacturer: Austin Semiconductor, Inc.

HARDWARE DATA PROTECTION
The command sequence requirement of unlock cycles
for programming or erasing provides data protection against
inadvertent writes (refer to Table 9 on page 21 for command
definitions). In addition, the following hardware data
protection measures prevent accidental erasure or
programming, which might otherwise be caused by
spurious system level signals during V
power-down transitions, or from system noise.
LOW V
When V
any write cycles. This protects data during V
and power-down. The command register and all internal
program/erase circuits are disabled, and the device resets.
Subsequent writes are ignored until V
V
control pins to prevent unintentional writes when V
greater than V
AS29LV016
Rev. 2.0 06/06
Table 8: Primary Vendor-Specific Extended Query
LKO
(Word Mode)
Addresses
. The system must provide the proper signals to the
4Ah
4Bh
4Ch
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
CC
CC
WRITE INHIBIT
is less than V
LKO
.
(Byte Mode)
Addresses
LKO
8Ah
8Ch
8Eh
80h
82h
84h
86h
88h
90h
92h
94h
96h
98h
, the device does not accept
Austin Semiconductor, Inc.
CC
CC
is greater than
0050h
0052h
0049h
0031h
0030h
0000h
0002h
0001h
0001h
0004h
0000h
0000h
0000h
power-up and
Data
CC
power-up
CC
Query-unique ASCII string "PRI"
Major version number, ASCII
Major version number, ASCII
Address Sensitive Unlock
0=Required, 1=Not Required
Erase Suspend
0=Not Supported, 1=To Read Only, 2=To Read and Write
Sector Protect
0=Not Supported, X=Number of Sectors Per Group
Sector Temorary Unprotect
00=Not Supported, 01=Supported
Sector Protect / Unprotect Scheme
01=29F040 mode, 02=29F016 mode,
03=29F400 mode, 04=29LV800A mode
Simultaneous Operation
00=Not Supported, 01=Supported
Burst Mode Type
00=Not Supported, 01= Supported
Page Mode Type
00=Not Supported, 01=4 Word Page, 02= 8 Word Page
is
16
WRITE PULSE GLITCH PROTECTION
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
LOGICAL INHIBIT
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
POWER-UP WRITE INHIBIT
If WE# = CE# = V
device does not accept commands on the rising edge of
WE#. The internal state machine is automatically reset
to reading array data on power-up.
IL
, CE# = V
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
BOO
BOOT SECT
BOO
BOO
BOO
IH
or WE# = V
Description
IL
T SECT
T SECTOR FLASH
T SECT
T SECT
and OE# = V
IH
. To initiate a write cycle,
IH
CO
COTS PEM
CO
CO
CO
OR FLASH
OR FLASH
OR FLASH
OR FLASH
during power up, the
AS29LV016
TS PEM
TS PEM
TS PEM
TS PEM