as29lv016brg-90/xt Austin Semiconductor, Inc., as29lv016brg-90/xt Datasheet - Page 18

• Manufacturer Part Number: as29lv016brg-90/xt
• Description: 16 Megabit 2m X 8-bit / 1m X 16-bit Cmos 3.0 Volt-only Boot Sector Flash Memory
• Manufacturer: Austin Semiconductor, Inc.

WORD/BYTE PROGRAM COMMAND
SEQUENCE
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Programming
is a four-bus-cycle operation. The program command
sequence is initiated by writing two unlock write cycles,
followed by the program set-up command. The program
address and data are written next, which in turn initiate
the Embedded Program algorithm. The system is not
required to provide further controls or timings. The device
automatically generates the program pulses and verifies
the programmed cell margin. Table 9 on page 21 shows
the address and data requirements for the byte program
command sequence.
When the Embedded Program algorithm is complete, the
device then returns to reading array data and addresses
are no longer latched. The system can determine the
status of the program operation by using DQ7, DQ6, or
RY/BY#. See Write Operation Status on page 22 for
information on these status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware
reset immediately terminates the programming operation.
The Byte Program command sequence should be
reinitiated once the device has reset to reading array data,
to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed from
a 0 back to a 1. Attempting to do so may halt the
operation and set DQ5 to 1, or cause the Data# Polling
algorithm to indicate the operation was successful.
However, a succeeding read will show that the data is
still 0. Only erase operations can convert a 0 to a 1.
UNLOCK BYPASS COMMAND SEQUENCE
The unlock bypass feature allows the system to program
bytes or words to the device faster than using the standard
program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock
cycles. This is followed by a third write cycle containing
the unlock bypass command, 20h. The device then enters
the unlock bypass mode. A two-cycle unlock bypass
program command sequence is all that is required to
program in this mode. The first cycle in this sequence
contains the unlock bypass program command, A0h; the
second cycle contains the program address and data.
Additional data is programmed in the same manner.
AS29LV016
Rev. 2.0 06/06
Austin Semiconductor, Inc.
18
This mode dispenses with the initial two unlock cycles
required in the standard program command sequence,
resulting in faster total programming time. Table 9 on
page 21 shows the requirements for the command
sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid.
To exit the unlock bypass mode, the system must issue
the two-cycle unlock bypass reset command sequence.
The first cycle must contain the data 90h; the second
cycle the data 00h. Addresses are don’t care for both
cycles. The device then returns to reading array data.
Figure 3 illustrates the algorithm for the program operation.
See Erase / Program Operations on page 32 for
parameters, and to Figure 16, on page 33 for timing
diagrams.
Note: See Table 9 on page 21 for program command
sequence.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Increment Address
BOO
BOOT SECT
BOO
BOO
BOO
Figure 3. Program Operation
in progress
Embedded
T SECT
T SECTOR FLASH
T SECT
algorithm
T SECT
Program
No
Command Sequence
Write Program
Last Address?
Programming
from System
CO
COTS PEM
CO
CO
CO
Verify Data?
OR FLASH
OR FLASH
OR FLASH
OR FLASH
Completed
Data Poll
START
AS29LV016
TS PEM
TS PEM
TS PEM
TS PEM
Yes
Yes
No