lc74772v Sanyo Semiconductor Corporation, lc74772v Datasheet - Page 7

• Manufacturer Part Number: lc74772v
• Description: Camcorder On-screen Display Lsi
• Manufacturer: Sanyo Semiconductor Corporation

First byte
Note: This register is set to 0 on a reset (either by the RST pin or by a command reset).
Notes on command settings
1. RSTSYS: A command reset is executed immediately after the data is read.
2. RAMCLR: The RAM can only be erased when display is off. This operation is not executed during display. This
3. OSCSTP: The LC oscillator stop command stops the LC oscillator connected to pins 2 and 3 (OSC
4. TSTMOD: The test mode command is executed if the TEST
DA0 to DA7
COMMAND 0 (System control setup 1)
The reset is cleared by returning the CS pin to high to reset this register. The reset is also cleared if this command is
executed consecutively or if this register is set to 0.
operation cannot be executed if the LC oscillator is stopped. Only use this command when the LC oscillator is
operating.
• This command bit is automatically cleared when the RAM erase operation completes.
• Once the RAM erase command has been read in, the following time is required to complete the operation.
The oscillator stop command is only executed when display is off. It is not executed if display is in progress.
• In external clock input mode, this command stops the acquisition of that clock signal.
by applications in normal operation.
— Tclear = 5 [µs] + 4/f
7
6
5
4
3
2
1
0
Register name
MOD
RAM
OSC
RST
SYS
CLR
STP
TST
—
—
—
—
State
OSC
0
0
0
0
0
1
0
1
0
1
0
1
(LC-oscillator) 288
Command 0 identification code
Normal operation
System reset
Normal operation
Normal operation VRAM clear (All data is set to FE (hexadecimal)) is stopped.
The LC oscillator operating state is maintained.
The LC oscillator is stopped.
Normal operation
Test mode
Register content
LC74772V
Function
IN
pin (pin 5) is high. This command should not be used
If CS is low, the reset is executed, but if
CS is high this command will be excluded.
The VRAM clear operation is not
executed when the oscillator
Valid when the display is off. VRAM write
is not possible when the oscillator is
stopped.
Illegal setting.
This bit must always be set to 0.
IN
Note
and OSC
No. 5159-7/17
OUT
).