IDT74SSTU32864 IDT [Integrated Device Technology], IDT74SSTU32864 Datasheet - Page 7

• Manufacturer Part Number: IDT74SSTU32864
• Description: 1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
• Manufacturer: IDT [Integrated Device Technology]

TERMINAL FUNCTIONS (ALL PINS)
NOTE:
1. The signals will be left unconnected.
ABSOLUTE MAXIMUM RATINGS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
2. The input and output negative voltage ratings may be exceeded if the ratings of the
3. This value is limited to 2.5V maximum.
IDT74SSTU32864/A
1:1 AND 1:2 REGISTERED BUFFER WITH 1.8V SSTL I/O
Symbol
V
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
I/P and O/P clamp current are observed.
V
T
CSR, DCS
V
V
O
I
Terminal
I
I
I
STG
OK
QCKEx
(2,3)
DD
IK
DD
RESET
QODTx
O
(2,3)
DCKE
QCSx
DODT
Name
GND
Z
Z
V
CLK
CLK
V
C x
Q x
OH (1)
Dx
OL (1)
REF
DD
Description
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Input Clamp Current
Output Clamp Current V
Continuous Output Current,
V
Continuous Current through each
V
Storage Temperature Range
O
DD
= 0 to V
or GND
Characteristics
LVCMOS Input
LVCMOS Input
Differential Input
Differential Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
1.8V nominal
0.9V nominal
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
Ground Input
Electrical
DD
Input
Input
V
V
V
I
I
O
O
< 0
> V
< 0
> V
Asynchronous Reset Input. Resets registers and disables V
DD
Description
Ground
Power Supply Voltage
Input Reference Voltage
Reserved for future use
Reserved for future use
Positive Master Clock Input
Negative Master Clock Input
Configuration Control Inputs
Chip Select Inputs. Disables outputs Dx switching when both inputs are HIGH.
Data Input. Clocked in on the crossing of the rising edge of CLK and the falling edge of CLK.
The outputs of this register bit will not be suspended by the DCS and CSR controls
The outputs of this register bit will not be suspended by the DCS and CSR controls
Data Outputs that are suspended by the DCS and CSR controls
Data Output that will not be suspended by the DCS and CSR controls
Data Output that will not be suspended by the DCS and CSR controls
Data Output that will not be suspended by the DCS and CSR controls
DD
–0.5 to V
–65 to +150
–0.5 to 2.5
–0.5 to 2.5
Max.
±100
±50
±50
±50
DD
+0.5
(1)
Unit
mA
mA
mA
mA
°C
V
V
V
7
REF
data and clock differential-input receivers.
COMMERCIAL TEMPERATURE RANGE