A40MX02-PL208A ACTEL [Actel Corporation], A40MX02-PL208A Datasheet - Page 8

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A40MX02-PL208A

Manufacturer Part Number
A40MX02-PL208A
Description
40MX and 42MX Automotive FPGA Families
Manufacturer
ACTEL [Actel Corporation]
Datasheet
Clock Networks
The 40MX devices have one global clock distribution
network (CLK). A signal can be put on the CLK network
by being routed through the CLKBUF buffer.
In 42MX devices, there are two low-skew, high-fanout
clock distribution networks, referred to as CLKA and
CLKB. Each network has a clock module (CLKMOD) that
can select the source of the clock signal from any of the
following
Figure 1-7 • Clock Networks of 42MX Devices
Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 1-8 • Quadrant Clock Network of A42MX36 Devices
1 -4
40MX and 42MX Automotive FPGA Families
• Externally from the CLKA pad, using CLKBUF
• Externally from the CLKB pad, using CLKBUF
• Internally from the CLKINTA input, using CLKINT
buffer
buffer
buffer
(Figure
1-7):
QCLKB
QCLKA
*QCLK1IN
*QCLK2IN
Modul
S0 S1
S0 S1
Quad
Quad
Modul
Clock
Clock
From
Pads
CLKB
CLKA
Drivers
Clock
QCLK1
QCLK2
CLKMOD
v3.1
The clock modules are located in the top row of I/O
modules. Clock drivers and a dedicated horizontal clock
track are located in each horizontal routing channel.
Clock input pads in both 40MX and 42MX devices can
also be used as normal I/Os, bypassing the clock
networks.
The A42MX36 device has four additional register control
resources, called quadrant clock networks
Each quadrant clock provides a local, high-fanout
resource to the contiguous logic modules within its
quadrant of the device. Quadrant clock signals can
originate from specific I/O pins or from the internal array
and can be used as a secondary register clock, register
clear, or output enable.
CLKINB
CLKINA
Clock Tracks
QCLK3
QCLK4
S0
S1
• Internally from the CLKINTB input, using CLKINT
buffer
CLKO(17)
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
Internal
Signal
S1
Modul
S1
Quad
Quad
Modul
Clock
Clock
S0
S0
*QCLK3IN
*QCLK4IN
QCLKC
QCLKD
(Figure
1-8).

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