A40MX02-PL208A ACTEL [Actel Corporation], A40MX02-PL208A Datasheet - Page 24

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A40MX02-PL208A

Manufacturer Part Number
A40MX02-PL208A
Description
40MX and 42MX Automotive FPGA Families
Manufacturer
ACTEL [Actel Corporation]
Datasheet
Sequential Timing Characteristics
Figure 1-21 • Input Buffer Delays
Note: D represents all data functions involving A. B. and S for multiplexed flip-flops.
Figure 1-23 • Flip-Flops and Latches
1 -2 0
40MX and 42MX Automotive FPGA Families
PRE, CLR
G, CLK
D
PAD
GND
Q
Y
E
1
PAD
t
INYH
1.5V
3V
INBUF
V
1.5V
50%
CCI
t
SUD
t
INYL
0V
Y
50%
CLK
(Positive Edge-Triggered)
D
E
t
WCLKA
t
SUENA
CLR
PRE
v3.1
Figure 1-22 • Module Delays
t
HD
t
CO
t
Y
HENA
S, A or B
t
WCLKI
Y
Y
t
WASYN
t PLH
50%
t PHL
50%
50%
50%
t
RS
PHL
t PLH
t
S
A
B
A
50%
50%
Y

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