A40MX02-PL208A ACTEL [Actel Corporation], A40MX02-PL208A Datasheet - Page 45

• Manufacturer Part Number: A40MX02-PL208A
• Description: 40MX and 42MX Automotive FPGA Families
• Manufacturer: ACTEL [Actel Corporation]

Table 1-14 • A42MX36 Timing Characteristics (Nominal 5.0V Operation)
Worst-Case Automotive Conditions, V
Parameter
Logic Module Combinatorial Functions
t
t
Logic Module Predicted Routing Delays
t
t
t
t
t
t
Logic Module Sequential Timing
t
t
t
t
t
t
t
t
t
Synchronous SRAM Operations
t
t
t
t
t
t
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
5. Delays based on 35 pF loading.
PD
PDD
RD1
RD2
RD3
RD4
RD8
RDD
CO
GO
SUD
HD
RO
SUENA
HENA
WCLKA
WASYN
RC
WC
RCKHL
RCO
ADSU
ADH
device performance. Post-route timing analysis or simulation is required to determine actual performance.
obtained from the Timer tool.
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
Internal Array Module Delay
Internal Decode Module Delay
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
Flip-Flop Clock-to-Output
Latch Gate-to-Output
Flip-Flop (Latch) Set-Up Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset-to-Output
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse Width
Flip-Flop (Latch) Asynchronous Pulse Width
Read Cycle Time
Write Cycle Time
Clock HIGH/LOW Time
Data Valid After Clock HIGH/LOW
Address/Data Set-Up Time
Address/Data Hold Time
PD1
3, 4
+ t
RD1
CCA
1
2
+ t
= 4.75V, T
Description
PDn
, t
CO
+ t
J
= 125°C
RD1
+ t
v3.1
PDn
, or t
PD1
+ t
RD1
+ t
40MX and 42MX Automotive FPGA Families
SUD
, whichever is appropriate.
Min.
11.3
11.3
0.0
1.1
0.0
5.5
7.2
0.6
5.7
2.7
0.0
Std. Speed
Max.
2.3
2.7
1.6
2.2
2.7
3.3
5.5
0.6
2.2
2.2
2.6
5.7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1-41