IDT70V9289L12PF IDT [Integrated Device Technology], IDT70V9289L12PF Datasheet - Page 6

• Manufacturer Part Number: IDT70V9289L12PF
• Description: HIGH-SPEED 3.3V 64K x18/x16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

Pin Names
Truth Table I—Read/Write and Enable Control
NOTES:
1. "H" = V
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4. LB and UB are single buffered regardless of state of FT/PIPE.
5. CEo and CE
6. I/O
7. I/O
R/W
I/O
CLK
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
CE
OE
A
UB
LB
ADS
CNTEN
CNTRST
FT/PIPE
0L
OE
X
X
X
X
X
X
H
0L
L
L
L
L
0L,
L
L
L
L
- A
L
8
0
Left Port
- I/O
CE
- I/O
- I/O
L
15L
L
L
IH,
1L
17L
CLK
7
15
"L" = V
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
(1)
for IDT70V9289.
for IDT70V9289.
1
are single buffered when FT/PIPE = V
IL,
V
V
CE
DD
SS
"X" = Don't Care.
X
H
L
L
L
L
L
L
L
L
R/W
I/O
CLK
CE
OE
A
UB
LB
ADS
CNTEN
CNTRST
FT/PIPE
0
(5)
0R
0R
R
0R,
R
R
R
R
R
Right Port
- A
- I/O
CE
CE
R
15R
X
R
L
H
H
H
H
H
H
H
H
R
1
1R
(5)
17R
(1)
UB
X
X
H
H
H
L
L
L
L
L
(4)
Chip Enables
Read/Write Enable
Output Enable
Data Input/Output
Clock
Upper Byte Select
Lower Byte Select
Counter Enable
Counter Reset
Flow-Through / Pipeline
Power (3.3V)
Ground (0V)
Address
Address Strobe Enable
LB
X
X
H
H
H
L
L
L
L
L
(4)
IL
. CEo and CE
Names
R/W
(3)
X
X
X
X
L
L
L
H
H
H
(2)
(2)
Upper Byte
DATA
DATA
1
4856 tbl 01
I/O
DATA
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
are double buffered when FT/PIPE = V
D
9-17
IN
OUT
OUT
IN
(6)
6.42
6
NOTE:
1. I/O
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE
CEo and CE
i.e. the signals take two cycles to deselect.
0
Lower Byte
X
DATA
DATA
I/O
DATA
DATA
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
- I/O
0-8
OUT
OUT
15
(7)
IN
IN
X
1
1
for IDT70V9289.
are single buffered when FT/PIPE = V
are double buffered when FT/PIPE = V
(1,2,3)
Industrial & Commercial Temperature Ranges
Deselected–Power Down
Deselected–Power Down
Both Bytes Deselected
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
IH
, i.e. the signals take two cycles to deselect.
MODE
IL
IH
,
,
4856 tbl 02