IDT70V65 IDT [Integrated Device Technology], IDT70V65 Datasheet - Page 16

• Manufacturer Part Number: IDT70V65
• Description: HIGH-SPEED 3.3V 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V
NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. If M/S = V
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = V
NOTES:
1. t
2. BUSY is asserted on port "B" blocking R/W
3. t
DATA
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
DATA
WH
WB
ADDR
ADDR
BUSY
L
must be met for both BUSY input (SLAVE) and output (MASTER).
is only for the 'slave' version.
R/W
= CE
OUT "B"
IN "A"
IL
for the reading port.
R
"A"
"A"
"B"
"B"
IL
= V
(slave), BUSY is an input. Then for this example BUSY
IL
.
t
APS
(1)
BUSY
R/W
R/W
"A"
"B"
"B"
"B"
, until BUSY
APS
is ignored for M/S = V
"B"
goes HIGH.
t
WB
(3)
t
BAA
"A"
= V
MATCH
IH
IL
t
and BUSY
16
WC
(SLAVE).
t
WP
(2)
"B"
t
WP
input is shown above.
MATCH
Industrial and Commercial Temperature Ranges
IL
t
DW
t
WDD
)
VALID
t
WH
(1)
4869 drw 13
t
DDD
(3)
t
BDA
t
DH
IH
4869 drw 12
t
BDD
)
VALID
(2,4,5)
.