IDT70V65 IDT [Integrated Device Technology], IDT70V65 Datasheet - Page 13

• Manufacturer Part Number: IDT70V65
• Description: HIGH-SPEED 3.3V 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
Timing Waveform of Write Cycle No. 2, CE Controlled Timing
NOTES:
1. R/W or CE or BEn = V
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = V
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
8. If OE = V
9. To access RAM, CE = V
CE or SEM
ADDRESS
CE or SEM
ADDRESS
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
DATA
(Figure 2).
placed on the bus for the required t
specified t
DATA
WR
DATA
is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
R/W
BEn
BEn
R/W
OUT
OE
IN
IN
(9)
IL
WP
(9)
(9)
(9)
during R/W controlled write cycle, the write pulse width must be the larger of t
.
IL
IH
transition occurs simultaneously with or after the R/W = V
IL
during all address transitions.
and SEM = V
t
AS
DW
EW
t
(6)
AS
. If OE = V
or t
(6)
IH
WP
. To access semaphore, CE = V
(4)
) of a CE = V
IH
during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
t
WZ
IL
and a R/W = V
(7)
t
t
AW
AW
t
t
WC
WC
t
EW
t
WP
(2)
(2)
IH
13
IL
and SEM = V
for memory array writing cycle.
IL
transition, the outputs remain in the High-impedance state.
t
t
DW
DW
IL
WP
. t
EW
or (t
must be met for either condition.
t
WZ
Industrial and Commercial Temperature Ranges
WR
+ t
(3)
DW
t
t
) to allow the I/O drivers to turn off and data to be
t
DH
DH
WR
t
OW
(3)
t
HZ
(7)
(1,5)
(4)
(1,5,8)
4869 drw 09
4869 drw 08