IDT70V3589 IDT [Integrated Device Technology], IDT70V3589 Datasheet - Page 12

• Manufacturer Part Number: IDT70V3589
• Description: HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
• Manufacturer: IDT [Integrated Device Technology]

Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE
NOTES:
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = V
3. The output is disabled (High-Impedance state) by CE
4. Addresses do not have to be accessed sequentially since ADS = V
5. If BE
6. "x" denotes Left or Right port. The diagram is with respect to that port.
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE
IDT70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Truth Table 1.
are for reference use only.
ADDRESS
DATA
n
ADDRESS
was HIGH, then the appropriate Byte of DATA
DATA
CLK
R/
CE
IL
CE
BE
OUT
OE
, CNTEN and REPEAT = V
W
0
1
n
(4)
CLK
R/
(1)
CE
CE
BEn
OUT
OE
W
'X'
"X"
0
1
(4)
(1)
= V
= V
t
t
t
t
SW
SC
SA
SB
An
IH
t
t
t
t
SC
SW
SB
SA
t
t
t
t
IL
HC
HB
HW
An
HA
)
(1 Latency)
(2)
)
t
t
CH2
t
t
t
HW
(2,6)
HC
HB
HA
IH
t
.
CH1
t
CKLZ
t
CYC2
t
t
CD1
CKLZ
t
CYC1
t
CL2
OUT
0
(1)
An + 1
t
= V
CL1
for Qn + 2 would be disabled (High-Impedance state).
IH
An + 1
, CE
1
t
CD2
Qn
= V
t
IL
DC
IL
constantly loads the address on the rising edge of the CLK; numbers
, BE
n
6.42
12
= V
IH
following the next rising edge of the clock. Refer to
t
An + 2
SB
(5)
Qn
An + 2
t
HB
t
DC
Qn + 1
t
OHZ
Industrial and Commercial Temperature Ranges
Qn + 1
t
OHZ
t
t
OE
OLZ
t
An + 3
SC
(3)
t
t
An + 3
SC
SB
t
(3)
HC
Qn + 2
t
t
HC
HB
t
t
OE
t
OLZ
DC
(5)
t
CKHZ
Qn + 2
5617 drw 06
5617 drw 07
(5)