IDT70V18L15PFI IDT [Integrated Device Technology], IDT70V18L15PFI Datasheet - Page 6

• Manufacturer Part Number: IDT70V18L15PFI
• Description: HIGH-SPEED 3.3V 64K x 9 DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

BUSY
DATA
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. t
4. Start of valid data depends on which timing becomes effective last t
5. SEM = V
6. Refer toTruth Table I - Chip Enable.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
IDT70V18L
High-Speed 3.3V 64K x 9 Dual-Port Static RAM
relation to valid output data.
BDD
ADDR
R/W
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
OUT
OUT
OE
CE
IH
.
(6)
CE
I
I
CC
SB
(6)
t
t
t
t
AA
ACE
AOE
LZ
Figures 1 and 2
(4)
(1)
GND to 3.0V
(4)
(4)
3ns Max.
t
PU
1.5V
1.5V
AOE
, t
4854 tbl 11
ACE
t
RC
50%
, t
AA
or t
t
6
BDD
BDD
DATA
(3,4)
.
BUSY
Figure 1. AC Output Load
OUT
INT
435
VALID DATA
Industrial and Commercial Temperature Ranges
t
PD
3.3V
4854 drw 03
590
30pF
(4)
50%
DATA
t
HZ
t
4854 drw 06
OH
(2)
OUT
Figure 2. Output Test Load
* Including scope and jig.
(for t
435
LZ
.
, t
HZ
, t
Preliminary
WZ
, t
4854 drw 05
3.3V
OW
4854 drw 04
)
590
5pF*