ADF4110 Analog Devices, ADF4110 Datasheet - Page 11

• Manufacturer Part Number: ADF4110
• Description: Single, Integer-N, 550 MHZ PLL With Programmable Prescaler And Charge Pump
• Manufacturer: Analog Devices

MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4110 family allows the
user to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2 and M1 in the function
latch. Table V shows the full truth table. Figure 6 shows the
MUXOUT section in block diagram form.
Lock Detect
MUXOUT can be programmed for two types of lock detect:
digital lock detect and analog lock detect.
Digital lock detect is active high. When LDP in the R counter
latch is set to 0, digital lock detect is set high when the phase
error on three consecutive Phase Detector cycles is less than 15 ns.
With LDP set to 1, five consecutive cycles of less than 15 ns
are required to set the lock detect. It will stay set high until a
phase error of greater than 25 ns is detected on any subsequent
PD cycle.
CP OUTPUT
R DIVIDER
N DIVIDER
R DIVIDER
N DIVIDER
HI
HI
D1
D2
CLR1
CLR2
U1
U2
Q1
Q2
PROGRAMMABLE
ABP1
UP
DOWN
DELAY
ABP2
U3
CPGND
V
P
CHARGE
PUMP
CP
ADF4110/ADF4111/ADF4112/ADF4113
The N-channel open-drain analog lock detect should be oper-
ated with an external pull-up resistor of 10 kΩ nominal. When
lock has been detected this output will be high with narrow low-
going pulses.
INPUT SHIFT REGISTER
The ADF4110 family digital section includes a 24-bit input shift
register, a 14-bit R counter and a 19-bit N counter, comprising
a 6-bit A counter and a 13-bit B counter. Data is clocked into
the 24-bit shift register on each rising edge of CLK. The data is
clocked in MSB first. Data is transferred from the shift register
to one of four latches on the rising edge of LE. The destination
latch is determined by the state of the two control bits (C2, C1)
in the shift register. These are the two LSBs DB1, DB0 as
shown in the timing diagram of Figure 1. The truth table for
these bits is shown in Table VI. Table I shows a summary of
how the latches are programmed.
C2
0
0
1
1
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
Control Bits
SDOUT
C1
0
1
0
1
Table I. C2, C1 Truth Table
MUX
Data Latch
R Counter
N Counter (A and B)
Function Latch (Including Prescaler)
Initialization Latch
CONTROL
DV
DGND
DD
MUXOUT