CT2553-FP AEROFLEX [Aeroflex Circuit Technology], CT2553-FP Datasheet - Page 25

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CT2553-FP

Manufacturer Part Number
CT2553-FP
Description
CT2553 / 2554 / 2555 / 2556 Advanced Integrated MUX (AIM) Hybrid FOR MIL-STD-1553
Manufacturer
AEROFLEX [Aeroflex Circuit Technology]
Datasheet
Aeroflex Circuit Technology
DBAC, RTU/BC, MT, CTLOUT B/A
SSFLAG, SSBUSY, SVCRQST
SYMBOL
tpw1
td1
td2
td7
td8
td9
tz
tr
16MHz Clock
(Internal)
MEM/REG
SELECT
READYD
D15-D00
STRBD
RD/WR
IOEN
A02
A01
A00
1. STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.
2. CPU must release STRBD within 1.5µs of IOEN going active. READYD will go away within one clock cycle maximum.
NOTE:
DESCRIPTION
READYD low delay (CPU Handshake)
IOEN high delay (CPU Handshake)
READYD pulse width (CPU Handshake)
Internal Register delay (write)
Register Data/Address set-up time
Register Data/Address hold time
READYD to STRBD release
(SELECT
Figure 28 – CPU Writes to Internal Register
See Note 1
CPU Writes to Internal Register
STRBD) to IOEN
tz
25
See Note 2
td1
td8
td7
DATA VALID
MIN
50
-
-
-
-
-
-
-
SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700
tr
tpw1
Configuration Register Only
MAX
1.37
150
1.8
20
60
30
DATA LATCHED
0
-
td9
UNITS
ns
ns
ns
ns
ns
ns
µs
µs
td2

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