CT2554 Aeroflex Circuit Technology, CT2554 Datasheet
CT2554
Related parts for CT2554
CT2554 Summary of contents
Page 1
... The CT2553 operates over the full military -55°C to +125°C temperature range. Available screened to MIL-STD883, the CT2553 is ideal for demanding military and industrial microprocessor to 1553 interface applications. See "Ordering Information" (last sheet) for CT2554, CT2555 & CT2556. echnology eroflex Circuit T ...
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... Aeroflex Circuit Technology 2 SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 ...
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... Control of the CT2553 is accomplished entirely through the use of three internal registers and the Aeroflex Circuit Technology Table 1 – CT2553 Specifications shared RAM. Transfers to and from the CT2553 are executed on a word-by-word basis ensuring ...
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... The host selects the Current Area by writing to the CT2553’s Configuration Register with bit 13 Aeroflex Circuit Technology set to the appropriate logic level (0 for area for area B). Internal circuitry ensures that the swapping of Current Area Status does not occur during an ongoing message transfer (See Configuration Register) ...
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... ROM RAM CPU ADDRESS DECODER HOST PROCESSOR Figure 2 – CT2553 Example Interconnection Aeroflex Circuit Technology RD/WR (DIR) DATA D15 (OE) (54LS245) I/O MEMENA-OUT (SEE NOTE 1) MEMENA-IN (OE) (54LS244) ADDRESS A12 A0 - A12 MSTRCLR POR (SEE NOTE 2) SELECT MEM/REG (54LS04) READYD MEMOE 16MHz CLOCK 5 RD/WR RTADP ...
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... MEMENA IN 69 Figure 3 – Internal Memory Only MEMENA IN 69 CT2553 A13 A14 A15 MEMENA OUT 31 Figure 5 – Configuration Using Both Internal and External Memory Aeroflex Circuit Technology CPU CT2553 MEMENA OUT 31 MEMENA IN 69 Figure 4 – External Memory Only ADDRESS BUS ...
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... Figure 6 – Use of Descriptor Stack – BC Mode CONFIGURATION STACK REGISTER POINTERS CURRENT AREA B Note: Figure 7 – Use of Descriptor Stack – RTU Mode Aeroflex Circuit Technology ** STACK DESCRIPTOR POINTERS STACKS * BLOCK STATUS WORD TIME TAG WORD RESERVED MESSAGE BLOCK ADDR MESSAGE COUNTER ...
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... In BC mode, It contains the address of the associated 1553 message (Data Block). In RTU mode, it contains the complete (received) 1553 Command Word. Aeroflex Circuit Technology STACK POINTER. A STACK POINTER (SP maintained at a specified location in shared RAM for each Descriptor Stack (SP-A: 0100H; SP-B: 0104H) ...
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... ADDRESS DATA BUS D15 - D00 Figure 10 – Example Configuration Using External Registers Aeroflex Circuit Technology DECODER A00 A A01 B EXTEN E A00 A B A01 E EXTLD Note: A02 of the CT2553 must be set to logic 1 to operate with external registers. Figure 9 – Use of External Registers 6 REGISTER ...
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... BC EOM Bus Controller End of Message. Set by the CT2553 following transmission of all messages within the current Message Block (Current area message count = FFFF). Figure 12 – Interrupt Mask Register Aeroflex Circuit Technology 15 RTU/BC MT CURRENT AREA B/A STOP ON ERROR BIT NAME ...
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... OFF-LINE TEST. The software-initiated Off-Line test can be executed only when the CT2553 is Aeroflex Circuit Technology configured as a BC. Set the Wrap-Around Test bit within the BC Control Word to a logic 1 and initiate any standard message transfer. This inhibits the 1553 transceivers and initiates the standard wrap-around test (i ...
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... BROADCAST COMMAND DATA WORD (NO DATA) 2 DATA WORD LAST DATA WORD LAST LOOPED BACK STATUS RECEIVE RECEIVE DATA BLOCK Aeroflex Circuit Technology CPU DATA BUS D15 - D00 Figure 15 – BC/RT Tagging (Optional) CONTROL CONTROL CONTROL WORD WORD WORD TRANSMIT RECEIVE MODE COMMAND COMMAND ...
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... Descriptor Stack A 0000-00FF Descriptor Stack B Aeroflex Circuit Technology ADDITIONAL FEATURES. The Configuration Register – STOP ON ERROR bit can be set. This causes the CT2553 to halt operation at the end of the current message transfer if an error is detected. In addition, setting the Interrupt Mask ...
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... READ CONTROL WORD TO DETERMINE TYPE OF TRANSFER TRANSFER DATA TO/FROM 1553 BUS UPDATE BLOCK STATUS WORD UPDATE TIME TAG INCREMENT STACK POINTER BY FOUR. DECREMENT MESSAGE COUNT Figure 17 – BC Sequence of Operation Aeroflex Circuit Technology YES DATA BLOCK TRANSFERRED OK TRANSFERRED STOP ON NO ERROR SET ? ...
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... COMPLEMENT OF MESSAGE COUNT = FD (HEX) LOAD START REGISTER WITH THE VALUE 02 Figure 18a – BC Set-Up Example for Two Message Transfer Aeroflex Circuit Technology 00FF. to RT# 1, Subaddress #1, Word Count = 1, transmitted on BUS A. RT#3, Subaddress #1, Word Count = 3, transmitted on BUS B. location 2001. START/RESET Register is memory mapped at location 2003. ...
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... Data Block 107 0000-00FF Descriptor Stack A 0F00-0FFF Descriptor Stack B Aeroflex Circuit Technology RTU LOOK-UP TABLE. The RTU mode uses a Look-Up Table in order to map the Data Blocks based upon incoming 1553 Command Words. The CT2553 uses the T/R and Subaddress fields to address the Look-Up Table. Each Look-Up ...
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... Generates an EOM or Error interrupt (if enabled). 2. Updates the Block Status Word: clears SOM, sets EOM, and any appropriate error bits. 3. Writes the Time Tag value into the Descriptor Stack. 4. Increments the Stack Pointer by 4. Aeroflex Circuit Technology RECEIVED COMMAND WORDS T/R SUBADD 0 00000 0 00001 ...
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... LMC SA/MC0-4, T/R ILLCMD SYMBOL DESCRIPTION t1 LMC to ILLCMD latch Figure 23 – Mode Command/Sub-Address Illegalization Timing Aeroflex Circuit Technology Error bit set. No data words are transmitted; received words, however, are placed in the Register bits. In shared RAM locations indicated by the current area Look-Up Table. ...
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... Command Sync and a RTU address equivalent to the RTAD0-RTAD4 inputs (pins 10, 9, 50, 49, and 11, respectively), THIS-RT (pin 55) will be pulsed low. This signal can be used to identify specific 1553 commands or for switching to RTU mode upon receipt of a command to this address. Aeroflex Circuit Technology Stack will Figure 24 – MT Initialization MSB 15 ...
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... Bits 8-9 are set by the mode command for Transmitter Shutdown and are cleared by the mode command for Override Transmitter Shutdown, Reset master RESET. Figure 27 – Built-In-Test Word (RTU Mode) Aeroflex Circuit Technology MT DATA STORAGE. Figure 26 shows the steps data Storage operation. ...
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... T/R bit Set to Zero. No status response. Bits set: message error (SW), T/R Error BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R Error (BIT Word). Aeroflex Circuit Technology Table 6 – Mode Codes 21 SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 ...
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... T/R bit Set to Zero. No status response. Bits set: message error (SW), Illegal Mode Code (BIT Word). 4. Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code (BIT Word). Aeroflex Circuit Technology Table 6 – Mode Codes (continued) 22 SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 ...
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... Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode Code, T/R Error, Low Word Count (BIT Word). 5. Broadcast Address. No status response. Bits set: message error, broadcast received (SW), Illegal Mode code, (BIT Word). Aeroflex Circuit Technology Table 6 – Mode Codes (continued) 23 ...
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... Command not Followed by Contiguous Data Word. No status response. Bits set: message error (SW), High word Count, Illegal Mode Code (BIT Word). 3. Command Followed by too many Data Words. No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code (BIT Word). Aeroflex Circuit Technology Table 6 – Mode Codes (continued) 24 SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 ...
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... Internal Register delay (write) td8 Register Data/Address set-up time td9 Register Data/Address hold time tr READYD to STRBD release (SELECT tz Figure 28 – CPU Writes to Internal Register Aeroflex Circuit Technology See Note 1 td1 See Note 2 tz td8 td7 DATA VALID CPU Writes to Internal Register STRBD) to IOEN • ...
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... Register Data/Address set-up time td9 Register Data/Address set-up time tpw6 EXTLD low pulse width tr READYD to STRBD release tz (SELECT Figure 29 – CPU Writes to External Register Aeroflex Circuit Technology See Note 1 td1 See Note 2 tz td8 VALID VALID td5 CPU DATA CPU Writes to External Register STRBD) to IOEN • ...
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... READYD pulse width (CPU Handshake) CPU MEMOE low delay td4 tr READYD to STRBD release tz (SELECT Figure 30 – CPU Reads from RAM Timing Aeroflex Circuit Technology See Note 1 See Note 2 tz td1 td4 RAM ADDRESS VALID RAM DATA VALID CPU Reads from RAM STRBD) to IOEN • ...
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... READYD pulse width (CPU Handshake) CPU MEMWR low delay td3 tpw2 CPU MEMWR low pulse width tr READYD to STRBD release tz (SELECT Aeroflex Circuit Technology See Note 2 tz td1 td3 RAM ADDRESS VALID RAM DATA VALID CPU Writes to Ram STRBD) to IOEN • ...
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... READYD pulse width (CPU Handshake) Register Data/Address set-up time td8 tr READYD to STRBD release tz (SELECT Figure 32 – CPU Reads from External Register Timing Aeroflex Circuit Technology td1 tz td8 DATA FROM EXTERNAL REGISTER CPU Reads from External Register Timing STRBD) to IOEN • 29 ...
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... READYD pulse width (CPU Handshake) Internal Register delay (read) td6 tr READYD to STRBD release tz (SELECT Figure 33 – CPU Reads from Internal Register Timing Aeroflex Circuit Technology See Note 1 td1 See Note 2 tz td6 DATA VALID CPU Reads from Internal Register STRBD) to IOEN • ...
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... TX/RX D01 (5) -0.4 42 D03 (5) -0.4 43 D05 (5) -0.4 44 D07 (5) -0.4 Aeroflex Circuit Technology (µA) I (mA -400 3.6 I/O Data Bus Bit 0 (LSB). -400 3.6 I/O Data Bus Bit 2. -400 3.6 I/O Data Bus Bit 4. -400 3.6 I/O Data Bus Bit 6. -400 3.6 I/O Data Bus Bit 8. -400 3.6 I/O Data Bus Bit 10. ...
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... Pin 13 = B6, Pin and Pin (MSB). B6, B7 and B8 are the MSB lines BIT Counter used in the BC and MT mode to count 32 WORD TRANSFERS to memory (16 words received off the bus) for a total of 128 DATA and Tag words (in MT mode). (See pages 19 & 20 for discussion.) Aeroflex Circuit Technology (µA) I (mA) ...
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... LOGIC +5V 54 SA/MC-3 15 SA/MC-1 55 THIS-RT 16 BCSTRCV 56 RTPARERR 17 LMC 57 T/R 18 -15VB 58 +5VB 19 GNDB 59 TX/RX-B 20 TX/RX-B DIP Pin Connection Diagram, CT2553 and Pinout Aeroflex Circuit Technology Table 7B – CT2553 Pin Out Description Pin Function # 1 D00 2 D02 3 D04 21 LOGIC GND 4 D06 60 A00 5 D08 22 A01 61 6 D10 A02 23 ...
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... THIS-RT 32 BCSTRCV 33 RTPARERR 34 LMC 35 T/R 36 -15VB 37 +5VB 38 GNDB 39 TX/RX-B 40 TX/RX-B 41 N/C Flat Package Pin Connection Diagram, CT2553 and Pinout Aeroflex Circuit Technology Table 8 – CT2566 Pin Out Description Pin Function # 1 N/C 2 D00 3 D01 82 N/C 4 D02 LOGIC GND 81 5 D03 A00 80 6 D04 A01 ...
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... Lead 1 & ESD Designator .100 .110 Pin 1 1.650 1.500 Pin 21 Pin 82 Lead 1 & ESD Designator Designator .400 MIN .095 (4 Places) Aeroflex Circuit Technology 2.100 1.900 Pin 2 Pin 19 .050 TYP Pin 41 Pin 60 .100 Pin 39 TYP Pin 22 1.800 Figure 23 – Plug In Package Outline 2.200 MAX ...
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... Model Number CT2553 CT2553-FP CT2554 CT2554-FP * CT2555 * CT2555-FP ** CT2556 ** CT2556-FP * Contact Factory ** Transceiverless – Contact Factory Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803 www.aeroflex.com/act1.htm Aeroflex Circuit Technology Ordering Information Screening Military Temperature, -55° ...