CT2553-FP AEROFLEX [Aeroflex Circuit Technology], CT2553-FP Datasheet
CT2553-FP
Related parts for CT2553-FP
CT2553-FP Summary of contents
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... All 1553 transfers are entirely memory-mapped; thus the CPU interface requires minimal hardware and/or software support. The CT2553 operates over the full military -55°C to +125°C temperature range. Available screened to MIL-STD883, the CT2553 is ideal for demanding military and industrial microprocessor to 1553 interface applications. See " ...
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... Aeroflex Circuit Technology 2 SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 ...
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... V 0.8 max V 16 MHZ +5±5% V -15±10% V -15±10% V +5±5% V +5±5% V (TYP)/max (85)/170 mA (45)/80 mA (85)/170 mA (80)/130 +125 ° +150 °C 2.1 x 1.87 x 0.25 in (53 x 47.5 x 6.4) (mm) 2.19 x 1.6 x 0.175 in (55.6 x 40.6 x 4.34) (mm) mods of operation SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 (1553 ...
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... CPU's data and address lines. External RAM can be used instead conjunction with the CT2553's internal bits. The external RAM used by the CT2553 can be any standard static memory with an access time of < 55ns. The external RAM can be expanded to 64K x 16. ...
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... RTADDRESS IOEN 73 TX/RX TX/RX BUS-25679 CT2553 TX/RX TX/RX BUS-25679 33 3 +5V STRBD 2 -15V 34 75 ILLCMD 12 INT 72 SA/MC-0 13 SA/MC-1 15 SA/MC SA/MC-3 ILLEGALIZATION 54 PROM SA/MC-4 (OPTIONAL T/R 57 BCSTRCV XX LMC 17 1553 INTERFACE SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 – – 4 +5V ...
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... ADDRESS BUS ADDRESS DECODER ADDRESS BUS 16 CS 64K x 16 STATIC RAM E ADDRESS DECODER 10K +5V CPU 16K STATIC RAM MAX SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 CPU ...
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... STACK POINTERS and LOOK-UP TABLE are switched via the CONFIGURATION REGISTER under external CPU control. DESCRIPTOR STACKS and DATA BLOCKS have 256 word boundries which should be observed DATA BLOCKS DATA BLOCK DATA BLOCK ** LOOK-UP TABLE DATA (DATA BLOCK ADDR) BLOCKS * DATA BLOCK DATA BLOCK SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 ...
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... RESPONSE TIME OUT (BC ONLY) CHB/CHA FORMAT ERROR (RTU ONLY) STATUS SET (BC ONLY) ERROR FLAG Note operation, the CT2553 always writes the BSW to RAM with Bit-13. CHB/CHA toggles as per the message control word setting. BIT NAME DEFINITION EOM Set at the completion of a message transfer regardless of whether any errors were detected ...
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... Figure 10 – Example Configuration Using External Registers Aeroflex Circuit Technology DECODER A00 A A01 B EXTEN E A00 A B A01 E EXTLD Note: A02 of the CT2553 must be set to logic 1 to operate with external registers. Figure 9 – Use of External Registers 6 REGISTER CPU 16 OE IOENBL 9 READ WRITE EXTLD 1 RTADP 5 RT ADDR ...
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... CURRENT AREA B/A Selects Current Area Pointers. RTU/BC Note: A logic 0 causes the corresponding bit within the RTU’s status word to be set to a logic 1. Figure 11 – Configuration Register START/RESET register is used to reset the CT2553 and to start the BC and MT operations, as illustrated in Figure 13 CONTROLLER START ...
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... The Status Word's Terminal Flag bit will be set to a logic fault was indicated by the wrap-around, self-test. OFF-LINE TEST. The software-initiated Off-Line test can be executed only when the CT2553 is Aeroflex Circuit Technology configured as a BC. Set the Wrap-Around Test bit within the BC Control Word to a logic 1 and initiate any standard message transfer ...
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... TIME TAGGING (OPTIONAL) The CT2553 will automatically access an external, 3-state device (i.e., counter) at the start and end of each message RTU modes. The CT2553 output, TAGEN (pin 76), enables the device's output onto the common, 16-bit data highway while executing a memory-write cycle. The device's value is written into the second location of the Descriptor Stack Entry ...
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... Aeroflex Circuit Technology ADDITIONAL FEATURES. The Configuration Register – STOP ON ERROR bit can be set. This causes the CT2553 to halt operation at the end of the current message transfer if an error is detected. In addition, setting the Interrupt Mask Register bits will result in a low pulse on the ...
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... UPDATE BLOCK STATUS WORD UPDATE TIME TAG INCREMENT STACK POINTER BY FOUR. DECREMENT MESSAGE COUNT Figure 17 – BC Sequence of Operation Aeroflex Circuit Technology YES DATA BLOCK TRANSFERRED OK TRANSFERRED STOP ON NO ERROR SET ? YES MORE MESSAGES TO SEND ? NO ISSUE BC EOM STOP 14 SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 YES ...
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... Stack Entries 01 80 0007 0000 0100 00FD 0101 00 80 0140 Message # 0180 Message # Left empty for RTU’s status response. ** Loop Back word. Figure 18c – BC SET-UP Memory Map SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 ...
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... START ISSUE RESET COMMAND INITIALIZE STACK POINTER SET UP LOOK-UP TABLE(S) DATA BLOCK ASSIGNMENTS SET UP DATA BLOCKS INITIALIZE INTERRUPT MASK REGISTER SET CONFIGURATION REGISTER TO RTU MODE START REGISTER WAIT FOR 1553 COMMAND Figure 19 – RTU Initialization SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 an ...
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... Look-Up Table. The MESSAGE TRANSFER CYCLE refers to the actual transfer of the 1553 message under control of the CT2553. The CT2553 transfers data to and from the memory on a word-by-word basis. Upon completion of the message transfer, the CT2553 executes an RTU End Of Message (EOM) cycle during which the CT2553: 1 ...
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... MIL-STD-1553 bus when busy upon receipt of a Transmit Command. VALID UNTIL NEXT VALID COMMAND WORD RECEIVED t1 LATCHED UNTIL NEXT VALID COMMAND WORD RECEIVED Mode Command Illegalization Timing 18 by decoding the word MIN MAX UNITS 250 - ns SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 ...
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... MT OPERATION Initiate a Reset in order to initialize the CT2553. Configure the CT2553 as a Bus Monitor (MT) by setting the appropriate Configuration Register Bits. See Figure 24 for MT initialization Steps. MT MEMORY CONFIGURATION. The user configures the memory by writing the start address for 1553 data storage into the Stack Pointer location ...
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... The Data Word and Identification Word transfers increment the counter by two. NO BUILT-IN-TEST WORD (RTU MODE) The CT2553 contains a 14 bit Built-In-Test (BIT) word register which stores information about the condition of the RTU. When a Mode Command is received to transmit BIT word, the contents of this register are transmitted over the 1553 data bus ...
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... This command is only used with dual redundant bus systems. The CT2553 responds with status. At the end of the status transmission, the CT2553 inhibits any further transmission from the dual redundant channel. Once shutdown, the transmitter can only be re-activated by Override Transmitter Shutdown or RESET RT commands. ...
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... Zero T/R bit and Broadcast Address. No status response. Bits set: message error, broadcast received (SW), T/R Error (BIT Word). RESERVED MODE CODES (01001-01111) MESSAGE SEQUENCE = RESERVED MODE CODES * STATUS The CT2553 responds with status. If the command is illegalized through an optional PROM, the message error bit is set and only the status word is transmitted. ERROR CONDITIONS 1 ...
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... MESSAGE SEQUENCE - TRANSMIT BIT WORD * STATUS BIT WORD The CT2553 transmits a status word followed by the BIT word . When activated, BITEN allows the subsystem to latch the BIT word on the parallel data bus. The BIT word is not altered by this command; however, the next SW will reflect errors in this transmission. ...
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... RESERVED MODE CODES MESSAGE SEQUENCE = RESERVED MODE CODE (T STATUS RESERVED MODE CODE (T STATUS The CT2553 responds with status. If the command was broadcast, the broadcast received bit is set and status transmission suppressed. ERROR CONDITIONS (T Invalid Command. No response, command ignored. 2. Command Followed by Data Word. No status response. Bits set: message error (SW), High Word Count, Illegal Mode Code (BIT Word) ...
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... See Note 1 td1 See Note 2 tz td8 td7 DATA VALID CPU Writes to Internal Register STRBD) to IOEN • td2 tpw1 DATA LATCHED Configuration Register Only td9 MIN MAX UNITS - 150 1.37 µs - 1.8 µs SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 ...
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... See Note 1 td1 See Note 2 tz td8 VALID VALID td5 CPU DATA CPU Writes to External Register STRBD) to IOEN • td2 td9 tpw1 tpw6 MIN MAX UNITS - 150 1.37 µs - 1.8 µs SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 ...
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... Figure 30 – CPU Reads from RAM Timing Aeroflex Circuit Technology See Note 1 See Note 2 tz td1 td4 RAM ADDRESS VALID RAM DATA VALID CPU Reads from RAM STRBD) to IOEN • td2 tpw1 MIN MAX UNITS - 150 100 ns - 1.37 µs - 1.8 µs SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 ...
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... See Note 2 tz td1 td3 RAM ADDRESS VALID RAM DATA VALID CPU Writes to Ram STRBD) to IOEN • Figure 31 – CPU Writes to RAM Timing 28 tr td2 tpw1 tpw2 MIN MAX UNITS - 150 - 120 1.37 - 1.8 SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 µs µs ...
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... Figure 32 – CPU Reads from External Register Timing Aeroflex Circuit Technology td1 tz td8 DATA FROM EXTERNAL REGISTER CPU Reads from External Register Timing STRBD) to IOEN • td2 tpw1 MIN MAX UNITS - 150 1.37 µs - 1.8 µs SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 ...
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... Figure 33 – CPU Reads from Internal Register Timing Aeroflex Circuit Technology See Note 1 td1 See Note 2 tz td6 DATA VALID CPU Reads from Internal Register STRBD) to IOEN • td2 tpw1 MIN MAX UNITS - 200 1.37 µs - 1.8 µs SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 ...
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... Table 7A – CT2553 Pin Function Table (78 Pin DIP) I (µA) I (mA) I Pin Name D00 (5) -0.4 2 D02 (5) -0.4 3 D04 (5) -0.4 4 D06 (5) -0.4 5 D08 (5) -0.4 6 D10 (5) -0.4 7 D12 (5) -0.4 8 D14 (5) -0.4 9 RTAD1 (5) -0.4 10 RTAD0 (5) -0.4 11 RTAD4 (5) -0.4 12 ILLCMD +10 ±0.01 13 SA/MC Logic + SA/MC BCSTRCV ...
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... Table 7A – CT2553 Pin Function Table (78 Pin DIP) (continued) I (µA) I (mA) I Pin Name D09 (5) -0.4 46 D11 (5) -0.4 47 D13 (5) -0.4 48 D15 (5) -0.4 49 RTAD3 (5) -0.4 50 RTAD2 (5) -0.4 51 RTADP (5) -0.4 52 SA/MC SA/MC SA/MC THIS- RTPARERR - - 57 T +5VB - - 59 TX/RX A00 (5) -0.4 61 A02 (5) -0.4 62 A04 (5) -0.4 63 A06 (5) -0 ...
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... EXTLD 29 A15 76 TAGEN 30 MEMOE 38 GNDA 31 MEMENA-OUT 77 +5VA 39 -15VA 32 CLOCK IN 78 TX/RX-A 33 MEM/REG 40 TX/RX-A 34 STRBD 35 EXTEN 36 RD/WR 37 EXTLD 38 GNDA 39 -15VA 33 SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 (DIP) Pin Function # 40 TX/RX-A 41 D01 42 D03 43 D05 44 D07 45 D09 46 D11 47 D13 48 D15 49 RTAD3 50 RTAD2 51 RTADP 52 SA/MC-2 53 SA/MC-4 54 SA/MC-3 55 THIS-RT ...
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... TAGEN 31 THIS-RT GNDA 47 32 BCSTRCV +5VA 46 33 RTPARERR -15VA 45 34 LMC TX/RX-A 44 TX/RX T/R N/C 42 -15VB 36 37 +5VB 38 GNDB 39 TX/RX-B 40 TX/RX-B 41 N/C 34 SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 (FP) Pin Function # 42 N/C 43 TX/RX-A 44 TX/RX-A 45 -15VA +5VA 46 47 GNDA 48 TAGEN 49 EXTLD 50 READYD 51 RD/WR 52 SELECT 53 EXTEN 54 IOEN 55 STRBD 56 INT 57 ...
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... MAX .050 .015 2.000 .050 Lead Centers 41 Leads/Side Figure 24 – Flat Package Outline 35 1.870 .250 MAX Pin 20 Pin 59 .018 DIA TYP Pin 78 Pin 40 .010 ±.002 Pin 42 .180 MAX 1.610 MAX MAX Pin 41 .080 SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700 .250 ...
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... Model Number CT2553 CT2553-FP CT2554 CT2554-FP * CT2555 * CT2555-FP ** CT2556 ** CT2556-FP * Contact Factory ** Transceiverless – Contact Factory Aeroflex Circuit Technology 35 South Service Road Plainview New York 11803 www.aeroflex.com/act1.htm Aeroflex Circuit Technology Ordering Information Screening Military Temperature, -55° ...