A43E26161G-95F AMICC [AMIC Technology], A43E26161G-95F Datasheet - Page 26

• Manufacturer Part Number: A43E26161G-95F
• Description: 1M X 16 BIT X 4 BANKS LOW POWER SYNCHRONOUS DRAM
• Manufacturer: AMICC [AMIC Technology]

(December, 2004, Version 1.0)
Page Read & Write Cycle at Same Bank @Burst Length=4
CLOCK
A10/AP
ADDR
(CL=2)
(CL=3)
CKE
RAS
CAS
BS0
BS1
DQM
CS
DQ
DQ
WE
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
0
Row Active
(A-Bank)
Ra
Ra
2. Row precharge will interrupt writing. Last data input, t
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
1
command to avoid bus contention.
before end of burst. Input data after Row precharge cycle will be masked internally.
2
t
RCD
3
(A-Bank)
Read
Ca
4
5
(A-Bank)
Read
Qa0
Cb
6
Qa1
Qa0
7
Qb0
Qa1
8
Qb0
Qb1
9
25
High
*Note1
RDL
Qb2
Qb1
10
before Row precharge, will be written.
11
(A-Bank)
Write
Dc0
Dc0
Cc
12
Dc1
Dc1
13
t
CDL
(A-Bank)
Write
Dd0
Dd0
Cd
14
AMIC Technology, Corp.
Dd1
Dd1
15
*Note3
t
*Note 2
RDL
16
Precharge
(A-Bank)
17
A43E26161
: Don't care
18
19