apu3073o APEC, apu3073o Datasheet - Page 3

• Manufacturer Part Number: apu3073o
• Description: Synchronous Pwm Controller With Over-current Protection / Ldo Controller
• Manufacturer: APEC

PARAMETER
Error Amp
Fb Voltage Input Bias Current
Fb Voltage Input Bias Current
V
Transconductance
Oscillator
Frequency
Ramp Amplitude
Output Drivers
Rise Time
Fall Time
Dead Band Time
Max Duty Cycle
Min Duty Cycle
LDO Controller Section
Drive Current
Fb Voltage
Input Bias Current
Thermal Shutdown
Current Limit
OC Threshold Set Current
OC Comp Off-Set Voltage
Note 1: Guaranteed by design but not tested in production.
PIN DESCRIPTIONS
PIN#
P
10
11
1
2
3
4
5
6
7
8
9
Voltage Range
PIN SYMBOL
SS / SD
Comp
Drv2
V
LDrv
Fb2
Fb1
Vcc
VcL
V
Rt
REF
P1
These pins provide feedback for the linear regulator controllers.
Outputs of the linear regulator controllers.
A resistor should be connected from this pin to ground for setting the switching frequency.
This pin provides soft-start for the switching regulator. An internal current source charges
an external capacitor that is connected from this pin to ground which ramps up the output
of the switching regulator, preventing it from overshooting as well as limiting the input
current. The converter can be shutdown by pulling this pin down below 0.4V.
Compensation pin of the error amplifier. An external resistor and capacitor network is
typically connected from this pin to ground to provide loop compensation.
This pin is connected directly to the output of the switching regulator via resistor divider to
provide feedback to the Error amplifier.
Non-inverting input of error amplifier.
Reference voltage.
This pin provides biasing for the internal blocks of the IC as well as powers the LDO
controller. A minimum of 1mF, high frequency capacitor must be connected from this pin
to ground to provide peak drive current capability.
This pin powers the low side output driver and can be connected either to Vcc or separate
supply. A minimum of 1mF, high frequency capacitor must be connected from this pin to
ground to provide peak drive current capability.
Output driver for the synchronous power MOSFET.
PIN DESCRIPTION
V
OC(OFFSET)
SYM
V
I
Freq
D
D
Drv1
OCSET
T
I
I
V
RAMP
FB1
FB2
Tr
Tf
MAX
MIN
DB
P
SS=3V
SS=0V
Note 1
Rt=100K
Rt=50K
Note 1
C
C
Fb=0.7V, Freq=200KHz
Fb=0.9V
Note 1
LOAD
LOAD
=1500pF
=1500pF
TEST CONDITION
0.784
180
340
MIN
0.8
35
85
40
20
-5
-1
-5
0
TYP
1.25
-0.1
-0.1
700
210
400
100
150
0.8
55
50
50
90
65
30
0
APU3073
0.816
MAX UNITS
240
460
100
100
1.5
+5
75
+1
40
+5
mmho
KHz
mA
mV
mA
mA
V
mA
mA
ns
ns
ns
%
%
8C
V
V
PP
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