w65c134s Western Design Center, Inc., w65c134s Datasheet - Page 34

• Manufacturer Part Number: w65c134s
• Description: W65c134s 8-bit Microcontroller
• Manufacturer: Western Design Center, Inc.

2.1
The WEB signal is high when the microprocessor is reading data from external memory or I/O and high
when it is reading or writing to internal memory or I/O. When WEB is low the microprocessor is writing
to external memory or external I/O. The WEB signal is bidirectional; when BE is low WEB is an input
for DMA operations to on-chip RAM or I/O.
microprocessor controls WEB.
2.2
2.3
PHI2 output is the main system clock used by the microprocessor for instruction timing, general on-chip
memory, and I/O timing. PHI2 also is used by the timers when enabled for counting PHI2 clock pulse.
The PHI2 clock source is either CLK or FCLK depending on the value of Timer Control Register One bit
1 (TCR11). When TCR11=0, then CLK is the PHI2 clock source. When TCR11=1, then FCLK is the
PHI2 clock source.
2.4
CLK and FCLK inputs are used by the timers for PHI2 system clock generation, counting events or
implementing Real Time clock type functions. CLK should always be equal to or less than one-fourth
the FCLK clock rate when FCLK is running (see the timer description for more information). CLKOB,
FCLKOB outputs are the inverted CLK and FCLK inputs that are used for oscillator circuits that employ
crystals or a resistor-capacitor time base. Timer Control Register One bit 1 (TCR11) selects if CLK
(TCR11=0) or FCLK (TCR11=1) is used as the PHI2 clock source.
WEB Write Enable (WEB) (active low)
RUN and SYNC outputs with WAI and STP defined (RUN)
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
Phase 2 Clock Output (PHI2)
Clock Inputs (CLK, FCLK), Clock Outputs (CLKOB, FCLKOB)
instruction. RUN is used to signal an external oscillator to start PHI2. The processor is
stopped when RUN is low.
multiplexed on RUN during PHI2 low time and RUN is multiplexed during PHI2 high time.
clock cycle. The ICE module demultiplexes RUN to provide full emulation capability for
the RUN function.
recommended PHI2 stop in the high state. When RUN goes high due to an enabled
interrupt or reset, the internal PHI2 clock is requested to start. The clock control function
is referred to as the RUN function of RUN.
enabled interrupt is requested or until RESB goes from low to high, starting the
microprocessor.
clock. RUN remains low and the clock remains stopped until an enabled interrupt is
requested or RESB goes from low to high.
When TCR12=0 (reset forces TCR12=0), FCLK is stopped. When TCR12=1, FCLK is
started.
milliseconds or an appropriate amount of time) for the oscillator to be stable before using
FCLK.
The RUN function of the RUN output is pulled low as the result of a WAI or STP
When BCR3=1 (ICE mode), the SYNC function (SYNC=1 indicates an opcode fetch) is
The BE input has no effect on RUN.
When RUN goes low the PHI2 signal may be stopped when high or low; however, it is
The WAI instruction pulls RUN low during PHI2 high time. RUN stays low until an
The STP instruction pulls RUN low during PHI2 high time and stops the internal PHI2
FCLK can be started or stopped by writing to Timer Control Register One (TCR12) bit 2.
When BCR3=0 (normal operating mode), the RUN function is output during the entire
When starting FCLK oscillator, the system software should wait (100
When BE is high during PHI2 low the internal
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