lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 31

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

13.4 Monitor Setup for Output Data Delay Setting (FSEL)
• Information available for delay setting of output data can be monitored by FSB0, FSB1 and DLMP pins by switching
• FSB0 and FSB1 terminal classifies the calculation result of the sampling frequency of input data into standard
• However, when S/PDIF data is not received, PLL is not locked, or when the mode 4 is set up with MODE0 and
• DLMP terminal outputs a pulse signal during the waiting time period at the time of ERROR flag switching, or during
the FSEL command. This setup is switched by FSEL command.
frequency, standard ×2, and standard ×4 and outputs.
MODE1 terminal, FSB0 and FSB1 terminals output low.
the mute period at the time of a delay setup. This pulse can change polarity by DLPO command.
(DLPO = 0)
DLMA to B
(XSTP = 0)
DLMX, Y
DATAO2
XSTATE
ERROR
DATAO
DLMP
State
State
Figure 13.10 Timing Chart for DLMP Output Mute Period (command cancel is not included)
FSB1 pin
H
H
L
L
Delay time
Recovery
Recovery
Mute
Table 13.3. FSB0 and FSB1 output state (FSEL = 1)
Delay setting of recovery data
FSB0 pin
SDIN
H
H
L
L
Mute = Delay time
Delay setting of SDIN
LC890561W
SDIN
S/PDIF data is not received, or PLL is unlocked, when the mode 4 is set up with
MODE0 and MODE1 terminal.
S/PDIF data is either of the 32kHz or 44.1kHz or 48kHz.
(Standard frequency)
S/PDIF data is either of the 88.2kHz or 96kHz.
(Standard × 2 frequency)
S/PDIF data is either of the 176.4kHz or 192kHz.
(Standard × 4 frequency)
SDIN
Mute
Output state
Recovery
Delay time
Recovery
Mute = Delay time
Recovery
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