lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet
lc890561w
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lc890561w Summary of contents
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... It supports sampling frequencies 192kHz replaceable with the existing LC89056W by devising the mounting board. The LC890561W has a build-in data buffer memory that allows a lip synchronization function. It allows the audio data output to be delayed after demodulation. The LC890561W is applicable to the reception of digital data transmission, such as AV amplifier, AV receiver and car audio. 1. Features • ...
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... Non-PCM burst preamble Pc data output. • 3.3V single source power supply. (Built-in 1.8V output regulator, 5V TTL interface is possible.) • Package: SQFP-48 2. Package Dimensions unit : mm 3163B 9.0 7 0.5 0.18 (0.75) SANYO : SQFP48(7X7) LC890561W 0.15 No8226-2/47 ...
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... LC890561W Figure 3.1 LC890561W Pin Assignment Table 4.1 Pin Functions AUDIO 24 23 EMPHA XIN 22 21 XOUT XMCK DGND 17 XSTATE DATAO 16 15 LRCK 14 BCK CKOUT 13 ...
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... Output clock selection input pin 48 XMODE I 5 System reset input pin Note: * Withstand voltage input/output -0.3 to 3.6V -0 prevent logic circuit latch-up, digital power supply and analog power supply must be applied or removed simultaneously and with the same potential. LC890561W Function No8226-4/47 ...
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... Pa,Pb detect Microcontroller C-bit detect Fs Calculation Demodulation & Lock detect Buffer RAM PLL Clock Selector CKSEL0 CKSEL1 XSTATE Figure 5.1 LC890561W Block Diagram F2/DLMP 27 F1/FSB1 28 F0/FSB0 34 ERROR Data 29 VF/DATAO2 Selector Data 16 DATAO Selector 8 SDIN 44 DOSEL0 45 DOSEL1 13 CKOUT 14 BCK 15 LRCK 48 XMODE ...
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... Supply Voltage Input Voltage Range 1 Input Voltage Range 2 Operating Temperature 6-2- and AV DD pins 6-2-2: DISEL, XIN, XSEL, MODE0, MODE1, DOSEL0, DOSEL1, CKSEL0 and CKSEL1 input pins 6-2-3: DN0, DIN1, DIN2, SDIN, DI, CE, CL and XMODE input pins LC890561W Symbol Conditions V DD 33max 6-1 6-1-2 ...
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... −8mA 8mA: DOUT, XOUT and XMCK output pins −4mA 4mA: BCK, LRCK, DATAO, VF/DATAO2 and F2/DLMP output pins −2mA 2mA: output pins other than those listed above 6-3- 25°C, input data fs = 96kHz 6-3-6: DIN0, DIN1 and DIN2 input pins LC890561W Symbol Conditions min V IH ...
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... XSEL = 0 (Except MODE0 = 1 and MODE1 = 1 setup) 6-4-3: XSEL = 1 (Except MODE0 = 1 and MODE1 = 1 setup) 6-4-4: XSEL = 1 (MODE0 = 1 and MODE1 = 1 setup) 6-4- 25° 3.3V (At the time of recommendation circuit setup) 6-4- input sampling frequency DIN0 to 2 BCK DATAO DATAO2 LRCK VF LC890561W Symbol Conditions min WDI t DUTY 6-4 6-4 ...
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... CSuw CSFLAG t BPdw BPSYNC CL (Normal H) CL (Normal DIdly open-drain output Figure 6.2 Microcontroller Interface AC Characteristics LC890561W Symbol Conditions min 6-5 6-5 setup t CE hold t DI setup t DI hold t CL setup ...
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... The proper PLL function to input over 96kHz will not be ensured when other frequency value is selected. • LPF is pin for loop filter of PLL and connects resistor and capacitor as shown below. LPF LC890561W 3. > 200µ Reset state System operation Figure 7.1 Reset Timing Chart ...
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... XADC command is output from XMCK. −The output of BCK and LRCK are as follows. Table 10.1 BCK and LRCK Outputs with Analog Source XIN pin 12.288MHz 24.576MHz 12MHz to 25MHz LC890561W C0 C1 10µF 0.1µF Figure 9.1 Composition of the regulator output BCK pin 3 ...
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... ERROR is output high even if PLL is locked. • In the input fs free mode, the reception range is set up without any restriction and fs calculation result is set so that it is not reflected in ERROR output. ERROR output will be set to low if PLL is locked. LC890561W Table 11.1 Setting operating mode MODE1 pin ...
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... The clock generated with XIN and XOUT is used for the following purposes. −Clock for detection of data input −Clock for A/D converter in analog source mode −Clock for calculation of input sampling frequency −Clock for PLL error lock countermeasure LC890561W Table 12.1 Data Input Pin Selection DISEL pin Input pin to be demodulated 0 ...
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... Also, the output polarity of XSATAE can be changed by the XSTP command. • All functions of a VCO oscillation clock and an oscillation amplifier can be stopped by the STOP command. At this time, all output clock terminals serve as DC output. LC890561W Table 12.2 XIN Supply Frequency Selection XSEL pin ...
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... XSTATE (XSTP = 0) ERROR CKOUT DIN0 to DIN2 Digital data PLL lock state XIN clock VCO clock XSTATE (XSTP = 0) ERROR CKOUT LC890561W Table 12.4 CKOUT Output Clock Selection CKSEL0 pin Digital data UNLOCK 1ms to 276ms (a): During lock-in phase LOCK 5ms to 12ms Same (b): During unlock phase Figure 12 ...
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... LRCK (O) BCK (O) DATAO (O) MSB DATAO2 (O) LRCK (O) BCK (O) DATAO (O) LSB DATAO2 (O) LRCK (O) BCK (O) DATAO (O) DATAO2 (O) LC890561W DOSEL0 pin 0 (0) 24bit MSB-first left justified 1 (1) 24bit MSB-first right justified 0 (2) 20bit MSB-first right justified 1 (3) 16bit MSB-first right justified L-ch LSB MSB Max. 24bit ...
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... Serial Audio Data Input Format (SDIN, DOSEL0, DOSEL1) • The LC890561W has SDIN which is serial digital audio data input pin and makes input of 24bit data possible. • The format of the serial audio data input into SDIN should be adjusted to the same format as the demodulated data output ...
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... Since DATAO2 shares the pin with the validity flag output, it should be changed by the VSEL command. The initial value of VSEL is the validity flag output. SDIN DIN0 DIN1 MUX (3in/1out) DIN2 LC890561W UNLOCK SDIN data Muted (a): Lock-in stage LOCK Demodulation data (b): Unlock stage ...
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... PLL lock error is performed. However, even if input data changes after ERROR goes low and the channel status information does not change the input data changes within the PLL capture range, ERROR does not go high. LC890561W NG OK ...
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... Input parity error (c): If occurred 8 times or fewer, in the case of Non-PCM burst data • Figure 12.7 shows an example of data processing upon occurrence of a parity error 1 occurrence Input data L-1 R-1 L-2 R-2 L-3 R-3 L-4 R-4 L-5 R-5 L-6 R-6 L-7 R-7 L-8 R-8 ERROR LRCK DATAO L-0 R-0 Figure 12.7 Example of Data Processing Upon Parity Error Occurrence (non delay setting) LC890561W Input parity error ( Output L Previous value data L Output ...
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... AUDIO outputs bit 1 of the channel status that indicates whether transfer data has PCM audio data or data other than audio. • AUDIO is output immediately after the detection of ERROR even during high output. AUDIO pin L H LC890561W 3ms to 300ms OK Output start from LRCK edge immediately after ERROR flag is lowered Table 12.7 EMPHA Output Output condition No pre-emphasis 50/15 µ ...
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... Pa, Pb, Pc and Pd are detected from the receive data even when an input parity error occurs. Input data 000h 000h LRCK DATAO BPSYNC Figure 12.10 Timing Chart for Pa, Pb, Pc and Pd Detection Signal Output LC890561W Table 12.9 CSFLAG Output Output condition Previous data current data are identical Previous data differs from current data bit 0 bit 0 ...
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... Note: *Output when PLL is unlocked or when a sampling frequency cannot be calculated. 12.13 Validity Flag Output (VF) • VF/DATAO2 outputs the validity flag. • VF/DATAO2 shares the pin with the demodulated audio data output pin (delay setup is impossible). Setting as VSEL=0 (default) makes output validity flag possible. VF pin LC890561W F0 pin Target fs frequency L Out of Range H ...
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... Max. (“○” can be set, “ ” maximum delay time is set) LC890561W Data fs after recovery processing (Hz) and setting commands 32k, 44.1k, 48k 88.2k, 96k (DTMA[4:0]) (DTMB[3:0]) ○ ○ ○ ○ ○ ○ ...
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... Max. (“○” can be set, “ ” maximum delay time is set) LC890561W SDIN input data fs (Hz) and setting commands 48k (DTMX[4:0]) (DTMY[3:0]) ○ ○ ○ ○ ○ ○ ○ ○ ...
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... Wn-2 Lock state Unlock ERROR XSTATE (XSTP = 0) DATAO2 SDIN data DATAO SDIN data Figure 13.2 Timing Chart for Output Data after Cancel of the Delay Time Setting During PLL Lock-in LC890561W Lock Same 0 data (mute data (mute) Wait period: 3ms to 300ms ...
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... Figure 13.4 Timing Chart for Output Data after Cancel of the Delay Time Setting During PLL Locked • When the command is changed before the completion of command setting, the delay process is initialized every command setting. For DATAO output, mute output is continued until the setting is fixed. LC890561W ex.) Delay = 70ms Rn ...
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... SDIN Ln-2 Rn-1 Ln-1 Lock state Lock ERROR XSTATE (XSTP = 0) DATAO2 Recovery data DATAO Recovery data Figure 13.6 Timing Chart for Output Data after Cancel of the Delay Time Setting During PLL Unlock LC890561W data (mute data (mute) Wait period: 5ms to 12ms ...
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... Figure 13.8 Timing Chart for Output Data after Cancel of the Delay Time Setting During PLL Unlock • When the command is changed before the completion of command setting, the delay process is initialized every command setting. For DATAO output, mute output is continued until the setting is fixed. LC890561W ex.) Delay = 50ms Rn ...
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... State of Commands LRCK Set-up of Commands DATAO Figure 13.9 Timing Chart from a Command Setup to Execution LC890561W 2 S data format setup) of LRCK clock. Therefore, the time lag DI0 DI1 DI2 DI12 DI13 DI14 DI15 ex.) Delay = 90ms Delay = 90ms Before (90ms) Time lag of command setting ...
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... DLMP (DLPO = 0) Delay time Mute Figure 13.10 Timing Chart for DLMP Output Mute Period (command cancel is not included) LC890561W FSB0 pin S/PDIF data is not received, or PLL is unlocked, when the mode 4 is set up with L MODE0 and MODE1 terminal. S/PDIF data is either of the 32kHz or 44.1kHz or 48kHz. ...
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... Figure 14.1 Input Timing Chart (Normal L Clock (pull up) Figure 14.2 Input Timing Chart (Normal H Clock Figure 14.3 Output Timing Chart (Normal L Clock, DO includes a pull-up resister) LC890561W Table 14.1 Addresses Settings CCB address 0xE8 0xE9 0xEA 0xEB 1 ...
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... ERR FSB0 FSB1 DO Update flag ERROR Figure 14.5 Output Timing of Flag + Channel Status Data 14.4 0xEA Data Output Timing CE DO Stream number CL Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 DO LC890561W DO0 DO1 DO2 MODE CATEGORY MODE 8bit Bit40 ...
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... DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 DI13 DI14 DI15 Note: * “0” reserved bit write-protected. LC890561W Table 14.2 Input Register Map Address: 0xEB 0 IMOD FSEL DOSW VSEL STOP CKPO SMOD 0 XCNT XSTP ...
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... System stop setting 0 1 SMOD Source setting 0 1 XCNT XIN, XOUT oscillation amplifier operation setting 0 1 XADC XMCK output clock setting 0 1 LC890561W CCB address: 0xE8 DI5 DI4 DI3 SMOD STOP DOSW DI13 DI12 DI11 ERF1 ERF0 FSL1 : Follow setting of DOSEL0 and DOSEL1 (default) ...
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... CKDV CKOUT output state setting when PLL is locked LC890561W Follow DISEL setting (default) Select DIN0 Select DIN1 Select DIN2 Normal mode (Same as the mode 1 of MODE0 and MODE1) (default) 32kHz to 48kHz Fs free mode A (Same as the mode 2 of MODE0 and MODE1) ...
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... XSTP XSTATE output polarity setting XCKS XMCK output setting while PLL is locked (Enable, when XCNT LC890561W CCB address: 0xEB DI4 DI3 CKPO VSEL DI12 DI11 0 DOM1 Data readout is performed with normal L clock (default) Data readout is performed with normal H clock F0, F1, F2 ...
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... Input fs 32kHz 44.1kHz 48kHz 88.2kHz 96kHz 176.4kHz 192kHz LC890561W Normal L output (default) Normal H output The data chosen by SMOD is outputted (default) Only DATAO is muted Only DATAO2 is muted DATAO and DATAO2 are muted Cancel error after preamble B is counted to 48 (default) Cancel error after preamble B is counted to 12 ...
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... The delay value at the time of 11010 setup is as follows. LC890561W CCB address: 0xEC DI4 DI3 DTMA4 DTMA3 DI12 DI11 0 DTMB3 : Non delay (default) : Delayed 10ms : Delayed 20ms ...
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... Delay time setting for DATAO output data Setup for 176.4kHz and 192kHz S/PDIF input data 000 001 010 011 100 101 110 111 The delay value at the time of 111 setup is as follows. LC890561W : Non delay (default) : Delayed 10ms : Delayed 20ms : Delayed 30ms : Delayed 40ms ...
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... The delay value at the time of 11010 setup is as follows. LC890561W CCB address: 0xED DI4 DI3 DTMX4 DTMX3 DI12 DI11 0 DTMY3 : Non delay (default) : Delayed 10ms : Delayed 20ms ...
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... The delay value at the time of 1101 setup is as follows. LC890561W : Non delay (default) : Delayed 10ms : Delayed 20ms : Delayed 30ms : Delayed 40ms : Delayed 50ms : Delayed 60ms : Delayed 70ms ...
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... DO22 C-bit14 DO23 C-bit15 DO24 C-bit16 DO25 C-bit17 DO26 C-bit18 DO27 C-bit19 LC890561W (Address: E9, Register: DO0) (Address: E9, Register: DO1) (Address: E9, Register: DO2, 3) (Address: E9, Register: DO4 to 7) (Address: E9, Register: DO8 to 55) (Address: EA, Register: DO0 to 15) Table 14.3 Read Data Address Register EA Pc-bit15 DO28 ...
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... DO22 Bit 14 DO23 Bit 15 DO24 Bit 16 DO25 Bit 17 DO26 Bit 18 DO27 Bit 19 DO28 Bit 20 DO29 Bit 21 DO30 Bit 22 DO31 Bit 23 LC890561W Contents Register Bit No. Application DO32 Bit 24 Control DO33 Bit 25 DO34 Bit 26 DO35 Bit 27 DO36 Bit 28 DO37 Bit 29 Not defined DO38 ...
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... Pc is output with MSB first • The latest data can be transferred by reading the falling edge of BPSYNC as the load enable signal. • The relation between the read register and burst preamble Pc data is shown below. LC890561W Table 14.5 Burst Preamble Pc data Register Bit No ...
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... C5 33pF** **Since the values of C5, R1, and R2 differ with an oscillator, please examine them enough. LC890561W LC890561W Data input A/D R0: 100Ω R1: 1MΩ** R2: 220Ω** R3 10kΩ ...
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... SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 2005. Specifications and information herein are subject to change without notice. LC890561W PS No8226-47/47 ...