lc890561w Sanyo Semiconductor Corporation, lc890561w Datasheet - Page 29

• Manufacturer Part Number: lc890561w
• Description: Cmos Digital Audio Interface Receiver With Built-in Data Buffer Memory
• Manufacturer: Sanyo Semiconductor Corporation

13.2.4 Output Data Delay Setup of SDIN Input Data (Setting at the state of ERROR = H)
• When the DTMX[4:0] or DTMY[3:0] commands are set up or changed during high output of ERROR flag, delay
• After power up, when the command is set up for the first time, a memory domain is assigned according to the set
• A memory domain is reset when the delay time is changed in the state where the command is already set up. And a
• Readout of the data written in the memory is started after the set delay time (frame).
• DATAO output is muted immediately after the command setup until the end of the set delay time.
• When delay time is canceled in the state where the command is already set up, the writing to the memory is stopped.
• When the command is changed before the completion of command setting, the delay process is initialized every
processing is performed according to the setup of those commands.
delay, and data is written in a memory.
memory domain is assigned according to the newly set delay time, and the data writing to a memory is started.
However, DATAO is output after muting the input data for 512-frame period. DATAO is not output immediately after
cancel of command setting. The 512-frame period is dependent on the sampling frequency of input data.
command setting. For DATAO output, mute output is continued until the setting is fixed.
(XSTP = 0)
Setting of
Delay time
Figure 13.7 Timing Chart for Output Data after Setup or Change of the Delay Time During PLL Unlock
Figure 13.8 Timing Chart for Output Data after Cancel of the Delay Time Setting During PLL Unlock
DATAO2
XSTATE
(XSTP = 0)
Setting of
Delay time
ERROR
DATAO
LRCK
DATAO2
XSTATE
ERROR
DATAO
LRCK
Lm-2
Ln-1
Lm-2
ex.) Delay = 50ms
Ln-1
ex.) Delay = 70ms
Rm-2
Rn-1
H
H
Rm-2
Rn-1
H
H
Lm-1
Ln
Lm-1
Ln
Rm-1
Rn
Rm-1
Rn
Ln+1
Lm
Ln+1
Lm
Rn+1
Rm
Rn+1
Rm
LC890561W
Ln+2
Ln+2
Rn+2
Rn+2
512-frame period (wait time)
Ln+3
Ln+3
0 data (mute)
Delay = 0ms
ex.) Delay = 50ms
Delay time (50ms)
0 data (mute)
Rn+a
Rn+a
Ln+b
Ln+b
Rn+b Ln+c Rn+c
Rn+b Ln+c Rn+c
Ln+c Rn+c
Ln-a Rn-a
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