cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 84
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cx28394
Manufacturer Part Number
cx28394
Description
Quad/x16/octal-t1/e1/j1 Framers
Manufacturer
Conexant Systems, Inc.
Datasheet
1.CX28394.pdf
(305 pages)
- Current page: 84 of 305
- Download datasheet (3Mb)
2.0 Circuit Description
2.3 System Bus
Figure 2-10. RSB 4096K Bus Mode Time Slot Interleaving
Figure 2-11. RSB 8192K Bus Mode Time Slot Interleaving
2-26
NOTE(S):
Output sync on rising edge clock, RSYN_NEG = 0 [addr 0D1]. RSBCKI operates at 1 times the data rate.
NOTE(S):
Output sync on rising edge clock, RSYN_NEG = 0 [addr 0D1]. RSBCKI operates at 1 times the data rate. RSB.OFFSET equals
zero.
RFSYNC
RSBCKI
RPCMO
RSIGO
RFSYNC
RSBCKI
RPCMO
RSIGO
A and B time slot comes from different framers. Output data on rising edge clock, RCPM_NEG = 0 [addr 0D1].
A, B, C, and D data comes from different framers. Output data on rising edge clock, RCPM_NEG = 0 [addr 0D1].
SIG31A
TS31A
SIG31A
TS31A
C, D) which allow multiple T1/E1 signals to share the same system bus. This is
done by interleaving the time slots from up to four framers, without external
circuitry (see
line rate and must be selected using the System Bus Interface Configuration
register [SBI_CR; addr 0D0].
SIG31B
TS31B
The 4.096 and 8.192 MHz bus modes contain multiple bus members (A, B,
SIG31C
TS31C
Figures 2-10
SIG31B
TS31B
Conexant
SIG31D
TS31D
and 2-11). The system bus rate is independent of the
SIG0A
TS0A
SIG0A
TS0A
SIG0B
TS0B
Quad/x16/Octal—T1/E1/J1 Framers
SIG0C
CX28394/28395/28398
TS0C
SIG0B
TS0B
SIG0D
TS0D
100054E
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