h5tq4g43mmr Hynix Semiconductor, h5tq4g43mmr Datasheet - Page 69

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h5tq4g43mmr

Manufacturer Part Number
h5tq4g43mmr
Description
4gb Ddr3 Sdram Ddp
Manufacturer
Hynix Semiconductor
Datasheet
Rev. 0.1 /Aug 2008
Figure 7 - Illustration of nominal slew rate and t
t
IS
Setup Slew Rate
Note: Clock and Strobe are drawn
(for ADD/CMD with respect to clock).
Falling Signal
V
V
V
V
on a different time scale.
V
IL(ac)
IL(dc)
REF(dc)
IH(dc)
IH(ac)
V
DDQ
DQS
DQS
CK
max
max
CK
min
min
V
SS
=
VREF to ac
V
region
REF(dc)
TF
∆TF
- V
tDS
IL(ac)
tVAC
tIS
nominal
slew rate
max
tDH
VAC
tIH
for hold setup t
Setup Slew Rate
Rising Signal
TR
DS
(for DQ with respect to strobe) and
tVAC
tIS
tDS
slew rate
nominal
=
V
IH(ac)
tIH
tDH
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
VREF to ac
min - V
region
∆TR
REF(dc)
69

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