h5tq4g43mmr Hynix Semiconductor, h5tq4g43mmr Datasheet - Page 5

• Manufacturer Part Number: h5tq4g43mmr
• Description: 4gb Ddr3 Sdram Ddp
• Manufacturer: Hynix Semiconductor

1. DESCRIPTION
The H5TQ4G43MMR-xxX and H5TQ4G83MMR-xxX are a 4,294,967,296-bit CMOS Double Data Rate III (DDR3) Synchro-
nous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
Hynix 4Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data
strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
1.1 Device Features and Ordering Information
1.1.1 FEATURES
Rev. 0.1 /Aug 2008
• VDD=VDDQ=1.5V +/- 0.075V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• On chip DLL align DQ, DQS and DQS transition with CK
• DM masks write data-in at the both rising and falling
• All addresses and control inputs except data,
• Programmable CAS latency 6, 7, 8, 9 and (10)
• Programmable additive latency 0, CL-1, and CL-2
• Programmable CAS Write latency (CWL) = 5, 6, 7
1.1.2 ORDERING INFORMATION
* xx means Binning grade (Speed/IDD...)
* X means Power Consumption & Temperature
H5TQ4G43MMR-xx*X
H5TQ4G83MMR-xx*X
transition
edges of the data strobe
data strobes and data masks latched on the
rising edges of the clock
supported
supported
Part No.
Configuration
512M x 4
256M x 8
82ball FBGA
Package
1.1.3 OPERATING FREQUENCY
Grade
-S6
-G7
• Programmable burst length 4/8 with both nibble
• BL switch on the fly
• 8banks
• 8K refresh cycles /64ms
• JEDEC standard 82ball FBGA(x4/x8)
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Write Levelization supported
• Auto Self Refresh supported
• On Die Thermal Sensor supported (JEDEC optional)
• 8 bit pre-fetch
sequential and interleave mode
CL5
O
CL6
O
O
Frequency [MHz]
CL7
O
CL8 CL9 CL10
O
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
DDR3-800 6-6-6
DDR3-1066 7-7-7
(CL-tRCD-tRP)
Remark
5