h5tq4g43mmr Hynix Semiconductor, h5tq4g43mmr Datasheet - Page 49
h5tq4g43mmr
Manufacturer Part Number
h5tq4g43mmr
Description
4gb Ddr3 Sdram Ddp
Manufacturer
Hynix Semiconductor
Datasheet
1.H5TQ4G43MMR.pdf
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Rev. 0.1 /Aug 2008
10. Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
For specific Notes See “Speed Bin Table Notes” on page 51.
Internal read command to
ACT to internal read or
ACT to PRE command
CL = 5
CL = 6
CL = 7
CL = 8
PRE command period
ACT to ACT or REF
command period
write delay time
Supported CWL Settings
Supported CL Settings
Parameter
first data
CL - nRCD - nRP
period
Speed Bin
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6
Symbol
t
t
t
t
t
t
t
t
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
CK(AVG)
t
t
RCD
t
t
t
RAS
RP
RC
AA
DDR3-1066 Speed Bins
13.125
13.125
13.125
50.625
1.875
1.875
37.5
min
2.5
DDR3-1066F
Reserved
Reserved
Reserved
Reserved
Reserved
6, 7, 8
7-7-7
5, 6
9 * tREFI
< 2.5
< 2.5
max
3.3
20
—
—
—
H5TQ4G43MMR-xxC
H5TQ4G83MMR-xxC
Unit
n
n
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CK
CK
1)2)3)4)6)
1)2)3)6)
1)2)3)4)
1)2)3)4)
1)2)3)
Note
4)
4)
4)
49
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