ax5042-1 AXSEM, ax5042-1 Datasheet - Page 26

• Manufacturer Part Number: ax5042-1
• Description: Rf Transceiver
• Manufacturer: AXSEM

26
Note: HDLC mode follows High-Level Data Link Control (HDLC, ISO 13239) protocol.
Circuit Description
The FIFO can be operated in polled or interrupt driven modes. In polled mode, the micro-
controller must periodically read the FIFO status register or the FIFO count register to
determine whether the FIFO needs servicing.
In interrupt mode EMPTY, NOT EMPTY, FULL, NOT FULL and programmable level interrupts are
provided. The
interrupt line is level triggered, active high. Interrupts are acknowledged by removing the
cause for the interrupt, i.e. by emptying or filling the FIFO.
Basic FIFO status (EMPTY, FULL, Overrun, Underrun, and the top two bits of the top FIFO word)
are also provided during each SPI access on MISO while the micro-controller shifts out the
register address on MOSI. See the SPI interface section for details. This feature significantly
reduces the number of SPI accesses necessary during transmit and receive.
HDLC Mode
HDLC Mode is the main framing mode of the AX5042. In this mode, the
automatic packet delimiting, and optional packet correctness check by inserting and
checking a cyclic redundancy check (CRC) field.
The packet structure is given in the following table.
Flag
8 bit
HDLC packets are delimited with flag sequences of content 0x7E.
In
(FCS) can be programmed to be CRC-CCITT, CRC-16 or CRC-32.
The receiver checks the CRC, the result can be retrieved from the FIFO, the CRC is
appended to the received data.
For details on implementing a HDLC communication see the
RAW Mode
In Raw mode, the
simply serialises transmit bytes and de-serializes the received bit-stream and groups it into
bytes.
This mode is ideal for implementing legacy protocols in software.
Version 2.2
AX5042
Address
8 bit
the meaning of address and control is user defined. The Frame Check Sequence
AX5042
8 or 16 bit
Control
AX5042
signals interrupts by asserting (driving high) its IRQ_TXEN line. The
does not perform any packet delimiting or byte synchronization. It
Information
Variable length, 0 or more bit in multiples of 8
AX5042
FCS
16 / 32 bit
Programming Manual.
AX5042
Datasheet AX5042
(Optional flag)
8 bit
performs