ax5042-1 AXSEM, ax5042-1 Datasheet
ax5042-1
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ax5042-1 Summary of contents
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... DATASHEET AX5042 Version 2.2 ...
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... Document Type Datasheet Document Status Document Version Version 2.2 Product AX5042 Version 2.2 Datasheet AX5042 ...
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... Crystal Oscillator ........................................................................................................................... 13 RF Frequency Generation Subsystem (Synthesizer) ................................................................ 14 Transmitter...................................................................................................................................... 15 Receiver ......................................................................................................................................... 16 SPI Timing........................................................................................................................................ 18 Wire Mode Interface Timing........................................................................................................ 18 5. Circuit Description ................................................................................................................... 19 5.1. Crystal Oscillator........................................................................................................................... 20 5.2. SYSCLK Output.............................................................................................................................. 20 5.3. PWRUP Input.................................................................................................................................. 20 5.4. RESET_N Input ................................................................................................................................ 21 5.5. DATA Input/Output and DCLK Output ..................................................................................... 21 5.6. RF Frequency Generation Subsystem....................................................................................... 22 VCO ................................................................................................................................................ 22 Version 2.2 3 Table of Contents Datasheet AX5042 ...
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... RX AGC and RSSI .................................................................................................................... 27 5.13. Modulator ................................................................................................................................ 28 5.14. Automatic Frequency Control (AFC) .................................................................................. 28 5.15. PWRMODE Register ................................................................................................................ 29 5.16. Serial Peripheral Interface (SPI) ............................................................................................ 31 SPI Timing........................................................................................................................................ 31 5.17. Wire Mode Interface.............................................................................................................. 32 Wire Mode Timing ......................................................................................................................... 32 6. Register Bank Description ....................................................................................................... 33 6.1. Control Register Map................................................................................................................... 34 7. Application Information.......................................................................................................... 37 7.1. Typical Application Diagram ..................................................................................................... 37 7.2. Antenna Interface Circuitry........................................................................................................ 38 Version 2.2 Datasheet AX5042 ...
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... Single-Ended Antenna Interface ............................................................................................... 38 Dipole Antenna Interface ........................................................................................................... 39 8. QFN28 Package Information .................................................................................................. 40 8.1. Package Outline QFN28 ............................................................................................................. 40 8.2. QFN28 Soldering Profile ............................................................................................................... 41 8.3. QFN28 Recommended Pad Layout ......................................................................................... 42 8.4. Assembly Process ......................................................................................................................... 42 Stencil Design & Solder Paste Application ............................................................................... 42 9. Life Support Applications ........................................................................................................ 44 10. Contact Information ................................................................................................................ 45 Version 2.2 5 Table of Contents Datasheet AX5042 ...
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... Telemetric applications, sensor readout • Toys • Wireless RS-232, USB • Access control • Remote keyless entry • ARIB compatible • Pointing devices and keyboards • Active RFID • RFID base station transmitter • 433/868/915 MHz SRD band systems Datasheet AX5042 ...
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... ANTP 4 5 ANTN PA F OUT Crystal Oscillator RF Frequency F XTAL typ. Generation 16 MHz Subsystem Divider Figure 1 Functional block diagram of the AX5042 Version 2.2 AX5042 Digital IF De- ADC channel modulator filter RSSI AGC Modulator Communication Controller & Chip configuration Block Diagrams ...
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... If the power-up/-down functionality is handled in software and no usage as general purpose I/O pin is planned then this pin should be tied to VDD Not to be connected Not to be connected Power supply Crystal oscillator input/output Crystal oscillator input/output I/O = digital input/output signal N = not to be connected P = power or ground Datasheet AX5042 ...
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... Pinout Drawing NC 1 VDD 2 GND 3 4 ANTP ANTN 5 GND 6 VDD 7 Version 2 DCLK 21 VDD 20 IRQ TXEN 19 AX5042 DATA 18 MOSI 17 MISO 16 CLK Figure 2: Pinout drawing (Top view) 9 Pin Function Descriptions Datasheet AX5042 ...
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... Input voltage digital pins V Electrostatic handling es Operating ambient T amb temperature T Storage temperature stg T Junction Temperature j Version 2.2 CONDITION MIN -0.5 -10 -100 -0.5 -0.5 HBM -2000 -40 -65 MAX UNIT +5 800 mW 15 dBm 10 mA 100 VDD+2.0V V VDD+3V V 2000 V 85 °C 150 °C 150 °C Datasheet AX5042 ...
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... MHz, 10 dBm 868 MHz, 4 dBm 868 MHz, 0 dBm 868 MHz, -12 dBm 433 MHz, 12 dBm 433 MHz, 6 dBm 433 MHz, 2 dBm 433 MHz, -8 dBm 11 Specifications MAX. UNIT 27 85 °C 2.5 2.8 V 0.5 µ Datasheet AX5042 ...
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... Input voltage, low IL V Input voltage, high IH I Input leakage current L DIGITAL OUTPUTS I Output Current, high OH I Output Current, low OL I Tri-state output leakage current OZ Version 2.2 CONDITION MIN. TYP. 1.9 1.2 2 -10 MAX. UNIT µ µA Datasheet AX5042 ...
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... XTALOSCGM =0010 3 default XTALOSCGM =0011 4 XTALOSCGM =0100 5 XTALOSCGM =0101 6 XTALOSCGM =0110 6.5 XTALOSCGM =0111 7 XTALOSCGM =1000 7.5 XTALOSCGM =1001 8 XTALOSCGM =1010 8.5 XTALOSCGM =1011 9 XTALOSCGM =1100 9.5 XTALOSCGM =1101 10 XTALOSCGM =1110 10.5 XTALOSCGM =1111 11 Note Specifications MAX. UNIT MHz mS MHz kΩ Datasheet AX5042 ...
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... MHz; 300 kHz from carrier 433 MHz; 2 MHz from carrier TYP. MAX. UNIT 16 MHz 930 MHz 470 MHz 1 Hz 100 50 kHz 200 500 15 30 µ µ -77 -75 -85 -100 dBc/Hz -85 -80 -90 -105 -65 -90 -105 -110 dBc/Hz -75 -80 -93 -115 Datasheet AX5042 ...
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... CONDITION MIN. TYP. ASK, PSK 0.1 FSK, MSK, OQPSK, 0.1 GFSK, GMSK TXRNG=0000 TXRNG=0001 -14 TXRNG=0010 -8 TXRNG=0011 -4 TXRNG=0100 -1 TXRNG=0101 0.5 TXRNG=0110 2 TXRNG=0111 3 TXRNG=1000 4 TXRNG=1001 5 TXRNG=1010 6 TXRNG=1011 7 TXRNG=1100 8 TXRNG=1101 8.5 TXRNG=1110 9 TXRNG=1111 10 TXRNG=1111 12 -50 Note 1 -55 Datasheet AX5042 15 Specifications MAX. UNIT 600 kbps 200 -50 dBm dBm dBc ...
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... TYP. MAX. UNIT 0.1 600 kbps 0.1 200 kbps -118 -111 -103 -101 -98 -119 -111 dBm -104 -101 -99 -101 -98 -96 -103 -118 -111 -104 -101 -99 -122 -115 dBm -107 -104 -100 -102 -99 -97 -99 -20 dBm -35 dBm - 0.625 dB 0 Datasheet AX5042 ...
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... MHz above the wanted signal Version 2.2 CONDITION MIN. FSK 50 kbps; notes 1 & 4 FSK 100 kbps ; notes 1 & 5 PSK 200 kbps; notes 1 & 6 FSK 4.8 kbps, notes 2 & Specifications TYP. MAX. UNIT Datasheet AX5042 ...
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... For a figure showing the wire mode interface timing parameters see section 5.17: Wire Mode Interface. Version 2.2 CONDITION MIN. TYP CONDITION MIN. TYP. Depends on bit 1.6 rate programming MAX. UNIT MAX. UNIT 10000 µ Datasheet AX5042 ...
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... In frame mode data is sent and received via the SPI port in frames. Pre- and postambles as well as checksums can be generated automatically. Interrupts control the data flow between a micro-controller and the AX5042. Both modes can be used both for transmit and receive. In both cases the as a SPI slave interface ...
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... The PWRUP pin disables all analog blocks when it is pulled low. If the pin is pulled high, then the power-up state of the analog blocks can be handled fully in software by programming register PWRMODE recommended to connect PWRUP to VDD. Version 2.2 PWRMODE register set the divider ratio. The output on pin SYSCLK can be register. After reset the Datasheet AX5042 ...
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... The DCLK output pin supplies the corresponding data clock which depends on the data-rate settings programmed to AX5042. In synchronous wire mode a connected micro-controller must receive or supply data on the DATA pin synchronous to the clock available the DCLK pin. In asynchronous wire mode, the receive/transmit clock is still available on the DCLK pin, but its usage is optional ...
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... The function is initiated by setting the RNG_START bit in the PLLRANGING register. The bit is readable and a 0 indicates the end of the ranging process. The RNGERR bit indicates the correct execution of the auto-ranging. Version 2.2 FREQ registers. For operation in the PLLLOOP register must be programmed. Datasheet AX5042 ...
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... The output power of the PA is programmed via bits TXRNG[3:0] in the register TXPWR. Output power as well as harmonic content will depend on the external impedance seen by the PA, recommendations are given in the section 7: Application Information. Version 2.2 Circuit Description PLLLOOP settings, for details see Datasheet AX5042 23 ...
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... These registers control the bit rate of the transmitter. These registers control the frequency deviation of the transmitter in FSK mode. The receiver does not explicitly need to know the frequency deviation, only the channel filter bandwidth has to be set wide enough for the complete modulation to pass. Datasheet AX5042 ...
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... HDLC and 802.15.4 modes. They are unused in Raw mode. The meta information consists of packet begin / end information and the result of CRC checks. The AX5042 contains one FIFO. Its direction is switched depending on whether transmit or receive mode is selected. Version 2.2 25 Circuit Description Datasheet AX5042 ...
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... HDLC Mode Note: HDLC mode follows High-Level Data Link Control (HDLC, ISO 13239) protocol. HDLC Mode is the main framing mode of the AX5042. In this mode, the automatic packet delimiting, and optional packet correctness check by inserting and checking a cyclic redundancy check (CRC) field. ...
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... RSSI value can be computed at the expense of a few arithmetic operations on the micro-controller. Formulas for this computation can be found in the AX5042 Programming Manual. Version 2.2 Circuit Description of the radio bit rate, however AGCCOUNTER TRKAMPL and the TRKAMPL registers, a high resolution 27 register. By Datasheet AX5042 ...
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... Bit = 1 Main lobe bandwidth PA on BW=BITRATE ∆f=+f BW=(1+h) ⋅BITRATE deviation ∆Φ=180 BW=BITRATE 0 AX5042 can demodulate signals with h < 4. AX5042 TRKFREQ to synchronize the receiver frequency TRKFREQ ∆ = • f BITRATE . 16 2 Max. bit rate 600kBit/s 200kBit/s 600kBit/s supports OQPSK. However, Datasheet AX5042 ...
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... Synthesizer and transmitter are running. Do not switch into this mode before the synthesizer has completely settled on the transmit frequency (in SYNTHTX mode), otherwise spurious spectral transmissions will occur. 29 Circuit Description PWRMODE and APEOVER Typical Idd 0.5 µA 650 µA 0.5 µ Datasheet AX5042 ...
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... POWERDOWN 2 STANDBY The settling time is dominated by the crystal used, typical value 3ms The synthesizer settling time is 5 – 50 µs depending on settings, see section AC 3 SYNTHRX Characteristics 4 FULLRX Data reception 5 POWERDOWN Version 2.2 sequence for a transmit session : sequence for a receive session : Datasheet AX5042 ...
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... Tssd Figure 3 Serial peripheral interface timing Version 2.2 AX5042 are programmed via the serial S3 S2 FIFO FULL FIFO EMPTY Tco 31 Circuit Description S1 S0 FIFOSTAT(1) FIFOSTAT(0) Tsh Tssz Datasheet AX5042 ...
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... AX5042 synchronizes the RS232 signal to its internal AX5042 are programmed via the serial peripheral interface (SPI). Tdck Tdch Tdcl Tds Tdh Tdco Figure 4 Wire mode interface timing AX5042 using register (recommended PINCFG2 inverts the DCLK AX5042 transmit and Datasheet AX5042 ...
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... No checks are made whether the programmed combination of bits makes sense! Bit 0 is always the LSB. Note Whole registers or register bits marked as reserved should be kept at their default values. Note All addresses not documented here must not be accessed, neither in reading nor in writing. Version 2.2 33 Register Bank Description Datasheet AX5042 ...
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... DCLKI IRQPTTI PWRUPI Pin Configuration 2 DCLKR IRQPTTR PWRUPR Pin Configuration 3 IRQINVERSION(3:0) IRQ Inversion MODULATION(3:0) Modulation ENC SCRAM ENC DIFF ENC INV Encoder/Decoder Settings FRMMODE(2:0) FABORT Framing settings CRC Initialisation Data CRC Initialisation Data CRC Initialisation Data CRC Initialisation Data Datasheet AX5042 ...
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... Transmitter Bit Rate Transmitter Bit Rate Transmitter Bit Rate PTTCLK – reserved Misc RF Flags GATE AGC Target Must be set to 0x0E AGC Attack AGC Decay AGC Current Value CIC Shifter – CICDEC(9:8) CIC Decimation Factor CIC Decimation Factor Data rate Data rate Datasheet AX5042 35 ...
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... TRKPHASE(11:8) Phase Tracking Phase Tracking Frequency Tracking Frequency Tracking reserved APE Overrride Synthesizer VCO current VCO_I(2:0) Leave at default Auto-ranging internal settings reserved PLLARNG PLLARNG must be set to 1 Reference adjust REF_I(2:0) Leave at default Misc RF settings RXIMIX(1:0) RXIMIX(1:0) must be set to 01 Datasheet AX5042 ...
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... VDD pin. In order to reduce noise on the antenna inputs it is recommended to add 27pF on the VDD pins close to the antenna interface. Version 2.2 Application Information N1 DCLK VDD VDD GND IRQ_TXEN AX5042 DATA ANTP ANTN MOSI GND MISO VDD CLK 37 GND Datasheet AX5042 ...
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... MHz 18 2.2 433 MHz 33 3 Version 2.2 AX5042 AX5042 is in transmit mode. A small antenna can be connected L3=L4 C2 C3=C5 [nH] [pF] [pF] 12 2.2 1.8 33 3.3 3 receive mode, and 50Ω single- CB ended equipment or antenna L5=L6 LB CA=CB C4=C6 [nH] [nH] [pF] [pF] 18 6.2 8.2 220 220 Datasheet AX5042 ...
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... Dipole Antenna Interface VDD L1 IC Antenna Pins L2 VDD Figure 7 Structure of the antenna interface to a dipole antenna Frequency L1=L2 Band [nH] 868 / 915 MHz 433 MHz Version 2.2 L3 dipole C2 C1 antenna L4 C1 L3=L4 [pF] [nH] 18 3.9 6 Application Information C2 [pF] 3.3 6.8 Datasheet AX5042 ...
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... Package surface shall be matte finish, Ra 1.6-2.2 9. Package warp shall be 0.050 maximum 10. Leadframe material is copper A194 11. Coplanarity applies to the exposed pad as well as the terminal 12. YYWWXX is the packaging lot code Version 2.2 AXSEM AX5042-1 YYWWXX Datasheet AX5042 ...
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... L Time Pb-Free Process 3 °C/sec max. T 150°C sMIN T 200°C sMAX t 60 – 180 sec s T 8min max. 25 ° to Peak T 217° – 150 sec L t 260° – 40 sec p 6°C/sec max. 41 Cooling Datasheet AX5042 ...
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... Clearance from edge of PCB thermal pad to PCB land, 0.2 mm minimum C = Clearance from PCB land edge to solder mask opening tight as possible to ensure that some solder mask remains between PCB pads D = PCB land length = QFN solder pad length + 0.1mm E = PCB land width = QFN solder pad width + 0.1 mm Datasheet AX5042 ...
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... No-clean flux is recommended since flux from underneath the thermal pad will be difficult to clean if water-soluble flux is used. Figure 9: Solder paste application on exposed pad Minimum 50% coverage Figure 10: Solder paste application on pins Version 2.2 QFN28 Package Information Maximum 62% coverage 80% coverage 43 Datasheet AX5042 ...
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... This product is not designed for use in life support appliances, devices systems where malfunction of this product can reasonably be expected to result in personal injury. AXSEM customers using or selling this product for use in such applications their own risk and agree to fully indemnify AXSEM for any damages resulting from such improper use or sale. Version 2.2 Datasheet AX5042 ...
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... Offenders will be held liable for the payment of damages. All rights reserved. Copyright © 2007 AXSEM AG Version 2.2 Contact Information Phone +41 44 882 17 07 Fax +41 44 882 17 09 Email sales@axsem.com www.axsem.com Datasheet AX5042 45 ...