mtsf1p02hdr2 Freescale Semiconductor, Inc, mtsf1p02hdr2 Datasheet - Page 6

• Manufacturer Part Number: mtsf1p02hdr2
• Description: Tmos Single P-channel Field Effect Transistor
• Manufacturer: Freescale Semiconductor, Inc

12) defines the maximum simultaneous drain–to–source vol-
tage and drain current that a transistor can handle safely
when it is forward biased. Curves are based upon maximum
peak junction temperature and a case temperature (T C ) of
25°C. Peak repetitive pulsed power limits are determined by
using the thermal response data in conjunction with the pro-
cedures discussed in AN569, “Transient Thermal Resistance
– General Data and Its Use.”
verse any load line provided neither rated peak current (I DM )
nor rated voltage (V DSS ) is exceeded, and that the transition
time (t r , t f ) does not exceed 10 s. In addition the total power
averaged over a complete switching cycle must not exceed
(T J(MAX) – T C )/(R JC ).
in switching circuits with unclamped inductive loads. For reli-
MTSF1P02HD
6
The Forward Biased Safe Operating Area curve (Figure
Switching between the off–state and the on–state may tra-
A power MOSFET designated E–FET can be safely used
0.01
100
0.1
10
1
0.1
Figure 12. Maximum Rated Forward Biased
V GS = 8 V
SINGLE PULSE
T C = 25°C
V DS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
R DS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
Safe Operating Area
dc
1
10 ms
1 ms
10
di/dt = 300 A/ s
Figure 11. Reverse Recovery Time (t rr )
SAFE OPERATING AREA
100
t, TIME
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction tem-
perature.
to–source avalanche at currents up to rated pulsed current
(I DM ), the energy rating is specified at rated continuous cur-
rent (I D ), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at cur-
rents below rated continuous I D can safely be assumed to
equal the values indicated.
Although many E–FETs can withstand the stress of drain–
360
320
280
240
200
160
120
Standard Cell Density
Motorola TMOS Power MOSFET Transistor Device Data
High Cell Density
80
40
0
25
t a
Figure 13. Maximum Avalanche Energy versus
t rr
t rr
t b
T J , STARTING JUNCTION TEMPERATURE (°C)
50
Starting Junction Temperature
75
100
125
V DD = 16 V
V GS = 5 V
L = 20 mH
I L = 6 A
150