mt58l512v18p ETC-unknow, mt58l512v18p Datasheet - Page 22

• Manufacturer Part Number: mt58l512v18p
• Description: 512k 256k 32/36 Pipelined, Syncburst Sram
• Manufacturer: ETC-unknow

GW#, BWE#,
BWa#-BWd#
READ TIMING PARAMETERS
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
SYMBOL
t
f
t
t
t
t
t
t
t
t
t
KC
KF
KH
KL
KQ
KQX
KQLZ
KQHZ
OEQ
OELZ
OEHZ
ADDRESS
(NOTE 2)
ADSP#
ADSC#
ADV#
OE#
CLK
CE#
Q
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q
4. Outputs are disabled within one clock cycle after deselect.
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
to be driven until after the following clock rising edge.
MIN
6.0
2.3
2.3
1.5
0
0
-6
t ADSS
MAX
t AS
t CES
166
3.5
3.5
3.5
3.5
A1
t ADSH
t AH
t CEH
t KH
(NOTE 3)
High-Z
t KC
MIN
7.5
2.5
2.5
1.5
t WS
0
0
t KL
-7.5
Single READ
t KQLZ
t WH
t KQ
MAX
133
4.0
4.2
4.2
4.2
t ADSS
A2
Q(A1)
MIN
t ADSH
3.0
3.0
1.5
1.5
10
0
t OEHZ
-10
t AAS
MAX
100
5.0
5.0
5.0
4.5
t AAH
t OELZ
t OEQ
READ TIMING
UNITS
(NOTE 1)
MHz
Q(A2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t KQX
t KQ
22
Q(A2 + 1)
PIPELINED, SCD SYNCBURST SRAM
SYMBOL
t
t
t
t
t
t
t
t
t
t
ADV#
suspends
burst.
AS
ADSS
AAS
WS
CES
AH
ADSH
AAH
WH
CEH
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
Q(A2 + 2)
MIN
BURST READ
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
-6
MAX
Q(A2 + 3)
MIN
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
-7.5
MAX
A3
Q(A2)
Burst continued with
new base address.
Burst wraps around
to its initial state.
DON’T CARE
MIN
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
Q(A2 + 1)
©2002, Micron Technology, Inc.
t KQHZ
Deselect
cycle.
-10
(NOTE 4)
MAX
UNDEFINED
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns