mt58l512v18p ETC-unknow, mt58l512v18p Datasheet - Page 20

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mt58l512v18p

Manufacturer Part Number
mt58l512v18p
Description
512k 256k 32/36 Pipelined, Syncburst Sram
Manufacturer
ETC-unknow
Datasheet
3.3V I/O AC TEST CONDITIONS
LOAD DERATING CURVES
SyncBurst SRAM timing is dependent upon the capaci-
tive loading on the outputs.
voltage curves.
8Mb: 512K x 18, 256K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L512L18P_C.p65 – Rev. 2/02
Input pulse levels .................. V
Input rise and fall times ..................................... 1ns
Input timing reference levels ...................... V
Output reference levels ............................ V
Output load ............................. See Figures 1 and 2
Micron 512K x 18, 256K x 32, and 256K x 36
Consult the factory for copies of I/O current versus
3.3V I/O Output Load Equivalent
3.3V I/O Output Load Equivalent
Q
Q
351
.................... V
Z = 50
O
Figure 1
Figure 2
+3.3V
V = 1.5V
IH
T
IL
317
5pF
= (V
= (V
50
DD
DD
/2.2) + 1.5V
/2.2) - 1.5V
DD
DD
Q/2.2
/2.2
20
PIPELINED, SCD SYNCBURST SRAM
2.5V I/O AC TEST CONDITIONS
Input pulse levels .............. V
Input rise and fall times ..................................... 1ns
Input timing reference levels ................... V
Output reference levels ............................... V
Output load ............................. See Figures 3 and 4
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2.5V I/O Output Load Equivalent
2.5V I/O Output Load Equivalent
Q
Q
225
................ V
Z = 50
O
Figure 3
Figure 4
+2.5V
IH
IL
V = 1.25V
= (V
T
= (V
225
5pF
DD
DD
©2002, Micron Technology, Inc.
/2.64) + 1.25V
50
/2.64) - 1.25V
DD
DD
/2.64
Q/2

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