hi-6110 Holt Integrated Circuits, Inc., hi-6110 Datasheet - Page 23

• Manufacturer Part Number: hi-6110
• Description: Bc / Rt / Mt Message Processor
• Manufacturer: Holt Integrated Circuits, Inc.

REGISTER FORMATS (MT Mode)
MSB
MSB
MSB
BIT
15-13
12
11
10 - 7
6
5 - 4
3 - 2
1
0
CONTROL REGISTER (R/W) Write Address: X1XX, Read Address: 1100
RECEIVE DATA FIFO (Read only) Read Address: 0100
BUS
BUS B WORD REGISTER (Read only) Read Address: 1010
15 14 13 12 11 10 9
15 14 13 12 11 10 9
15 14 13 12 11 10 9
X
A WORD REGISTER
X
NAME
CLKSEL
Reserved
RERR
MRB, MRA Setting either MRA or MRB to "1"connects the
RTMODE, HI-6110 mode select. These Control Register bits are logically OR'ed with their corresponding input pins. The
BCMODE
-
MR
-
RA3:0
X
MIL-STD-1553 Message Data Word 15:0
0
FUNCTION
Not used in MT mode.
Selects the frequency of the HI-6110 external CLK input, as follows:
CLKSEL
0
1
Must be reset to “0”
Register Address for HI-6110 register and data read / write operations. The register address is defined by the
logical OR of these bits and their corresponding input pins. Setting Control Register bits 10:7 to 0000 ensures
that just the address input pins control register addressing.
Reset ERROR. If RERR is low the ERROR output signal is only reset on reception of a new valid
Setting RERR high
automatically reset after 3 to 4 microseconds. For normal operation, this bit is set to “1”.
both MRA and MRB selects neither bus.
remain operational on the inactive bus. When the monitor terminal receives a command on the inactive bus, its
RCV signal output goes high. The MT must switch active buses so received data words, message results, etc.
will be stored in the proper registers. V
active bus by reading the Bus A Word or Bus B Word Register, but any received message words, errors, message
results etc. are not updated if the bus is not enabled by setting the appropriate MRA or MRB bit.
user can select 1553 operating mode under either hardware or software control:
RTMODE
0
1
1
0
Not used in MT mode.
Master Reset. Writing "1" and then “0” to this bit performs the same function as pulsing the MR pin. All register
and data FIFOs are cleared when master reset is asserted. The Control Register is the exception; it is not
affected by Master Reset.
Bus A/B Word 15:0
8
(Read only) Read Address: 1001
8
8
7
7
7
Value
24 MHz
12 MHz
BCMODE 1553 OPERATING MODE
1
0
1
0
6
6
6
(rising edge)
5
HI-6110 (BUS MONITOR MODE)
5
5
4
4
4
HOLT INTEGRATED CIRCUITS
Bus Controller (BC)
Remote Terminal (RT)
Bus Monitor without assigned RT address (MT)
Bus Monitor with assigned RT address (RT-MT) in which Control Register bits
5:4 enable transmit for valid commands for which command terminal address matches
the assigned Remote Terminal address. See the RT mode section.
3
3
3
2
2
2
resets a high ERROR output .
1
1
X
1
0
0
0
alid words received on the inactive bus can be read without changing
LSB
LSB
LSB
23
The 1553 receiver, Manchester decoder and RCV output signal
protocol engine
The Control Register value specifies HI-6110 operating mode,
clock frequency and specifies which bus is enabled for
monitoring. Control Register bits can also be used for
addressing registers in read/write operations, or to assert
master reset.
The Receive Data FIFO is 32-words deep and holds all MIL-
STD-1553 received data words. The FIFO is cleared at Master
Reset.
A low FFEMPTY flag (output pin or Status register bit) means
FIFO data is available to be read by the host. Successive data
word fetches will cause FFEMPTY to go high when the last
data word is read.
In MT mode, the Bus A Word register holds the last valid MIL-
STD-1553 word received on Bus A. The Bus B Word register
holds the last valid MIL-STD-1553 word received on Bus B.
If the RERR bit is left high, ERROR outputs will
to Monitor BUS A or Monitor BUS B.
command.
Setting