hi-6110 Holt Integrated Circuits, Inc., hi-6110 Datasheet - Page 22

• Manufacturer Part Number: hi-6110
• Description: Bc / Rt / Mt Message Processor
• Manufacturer: Holt Integrated Circuits, Inc.

BUS MONITOR
The HI-6110 may be configured as Bus Monitor with or without an
assigned RT address. Resetting both BCMODE and RTMODE to
“0” configures the HI-6110 as a Bus Monitor with assigned RT
address (MT/RT mode). Setting both BCMODE and RTMODE to
“1” configures the HI-6110 as a Bus Monitor without an RT address
(MT mode). In either Mode, the HI-6110 captures all information
that occurs on the selected MIL-STD-1553 bus. All bus
transactions are checked for errors. If a message sequence is
good, the VALMESS signal is asserted at the end of the message. If
an error occurs, ERROR is asserted. The host may interrogate the
ERROR Register to determine the nature of the error. Command
Words, Status Words, Message Data and Mode Words are
captured for all bus transactions and may be read by the host.
In MT/RT mode, the HI-6110 will respond to all MIL-STD-1553
messages with assigned RT address matching the pin-
programmed RT address. All conditions pertinent to RT responses
are described in the previous Remote Terminal Mode section of this
document.
RCVCMDA
RCVCMDB
FFEMPTY
VALMESS
BCSTART
BCMODE
RTMODE
RA3-RA0
ERROR
D15-D0
RFLAG
RCVB
RCVA
STR
R/
CLK
MR
CS
W
Message
Interface
Protocol
Control
Status
Host
Data
Figure 3. Block Diagram - Bus Monitor (without assigned RT address) Mode
Message Register
MT Error Register
Control Register
Status Register
HI-6110 (BUS MONITOR MODE)
Status Word Rec'd
Command Word 1
Command Word 2
Receiving Status
Mode Data (R)
Word (RT-RT)
HOLT INTEGRATED CIRCUITS
DATA
FIFO
RX
MT Protocol Engine
22
In MT mode (no assigned RT address), the HI-6110 does not
transmit information to the MIL-STD-1553 bus and acts as a
passive monitor as described by the MIL-STD-1553 specification.
Figure 3 represents the HI-6110 in MT mode.
INITIALIZATION
In Bus Monitor mode, the user must first perform Master Reset to
initialize the MT protocol engine and clear all message registers
and data FIFOs. This may be achieved by pulsing the MR input
high, or writing a "1" to Control Register bit 0. The user must select a
master clock (CLK) frequency by programming Control Register
bits 11 and 12. Refer to the MT Register Formats section for a full
description of available registers and their functions in Bus Monitor
Mode.
In MT mode (without assigned RT address) the five RT Address
input pins RTA0 to RTA4 must be pulled high or left unconnected. In
the second case, internal pull-up resistors act to hold the five RTA
inputs high. In MT mode, the RTAP pin is “don’t care”.
Bus B Word
Bus A Word
Parallel
Parallel
Serial
Serial
to
to
Manchester
Manchester
Decoder
Decoder
Receiver
Receiver
BUSA
BUSA
BUSB
BUSB
Bus A
Bus B