hi-6110 Holt Integrated Circuits, Inc., hi-6110 Datasheet - Page 13

• Manufacturer Part Number: hi-6110
• Description: Bc / Rt / Mt Message Processor
• Manufacturer: Holt Integrated Circuits, Inc.

REGISTER FORMATS (RT Mode)
MSB
MSB
MSB
BIT
15
14
13
12
11
10 - 7
6
5 - 4
3 - 2
1
0
TRANSMIT DATA FIFO (Write only) Write Address: X011
BUS
BUS B WORD REGISTER (Read only) Read Address: 1010
CONTROL REGISTER (R/W) Write Address: X1XX, Read Address: 1100
15 14 13 12 11 10 9
X
15 14 13 12 11 10 9
15 14 13 12 11 10 9
R
A WORD REGISTER
ESET TRANSMIT DATA
NAME
-
REPTO
CLKSEL
Reserved
RA3:0
RERR
TRB, TRA
RTMODE,
BCMODE
-
MR
IDWT
MIL-STD-1553 Message Data Word 15:0
0
FUNCTION
Not used.
Controls the time-out which causes the No Response Error.
Selects the frequency of the HI-6110 external clock input.
CLKSEL equals “1” selects a 12 MHz clock.
This bit must be reset to “0”
Register Address for HI-6110 register and data read / write operations. The register address is defined by
the logical OR of these bits and their corresponding input pins. Setting Control Register bits 10:7 to 0000
ensures that only the input pins are used for addressing registers.
Reset ERROR. If RERR is low, the ERROR output pin can only be reset by asserting MR, master reset. Writing
RERR high causes the ERROR output to be reset (rising edge). If the RERR is left high, the ERROR output
will automatically reset after 3 to 4 microseconds. For normal operation, this bit is set to “1”.
Setting either TRA or TRB to "1" enables transmission on MIL-STD-1553 BUS A or BUS B. Setting both TRA and
TRB selects neither bus. The RT protocol engine connects to the selected, active bus. The 1553 receiver,
Manchester decoder and RCV output signal are still operational on the inactive bus. This is useful when the
remote terminal receives a command on the inactive bus, indicated by RCV signal output. The RT must switch
active buses to service the command. Valid words received on the inactive bus can be read without changing
active bus by reading the Bus A Word or Bus B Word register, but the terminal cannot respond as transmit is
disabled. NOTE: the TXINHA and TXINHB input pins can override bus enablement.
HI-6110 mode select. These Control Register bits are logically OR'ed with their corresponding input pins,
allowing the user to select 1553 operating mode under either hardware or software control:
Not used in RT mode.
Master Reset. Writing "1" and then “0” to this bit performs the same function as pulsing the MR pin. All registers
and data FIFOs are cleared when master reset is asserted. The Control Register is the exception; it is not
affected by master reset.
Inhibit Data Word Transmission. When “illegal command detection” is required, this feature alows
“command illegalization”. When the IDWT bit is set, normal transmission of ordinary and mode data words is
suppressed for all transmit commands. NOTE: There will be no VALMESS or ERROR assertion for the affected
message. For normal response to the next command, this bit must be reset before that command’s Status
Word bit 0 is transmitted.
Bus A/B Word 15:0
RTMODE
0
1
0
0
1
1
8
8
(Read only) Read Address: 1001
8
7
7
7
FIFO
6
HI-6110 (REMOTE TERMINAL MODE)
6
6
17 usec Gap (equivalent to the 57 usec measurement of 5.2.1.7 of the RT Validation Test Plan)
131 usec Gap
BCMODE
5
5
Write Address: X010
5
0
1
0
1
4
4
4
HOLT INTEGRATED CIRCUITS
1
3
3
3
0
2
2
2
1553 OPERATING MODE
Bus Monitor (MT), with assigned RT address
Bus Controller (BC)
Remote Terminal (RT)
Bus Monitor (MT), without assigned RT address
X
1
1
1
0
0
0
LSB
LSB
LSB
13
The Control Register value specifies HI-6110 operating mode,
clock frequency and the bus enabled for transmit. It can also
be used to address registers for read/write operations, assert
master reset, as well as data word suppression when illegal
command detection is implemented .
The 32-word Transmit Data FIFO holds MIL-STD-1553
message data.
into the FIFO before mid-parity bit transmission for the
preceding MIL-STD-1553 word occurs. Words are transmitted
in the order loaded.
assertion of VALMESS or ERROR outputs, or by any write to
register address X010. See section, “AC Electrical
Characteristics” for special timing requirements when writing
to register address X010 to reset the FIFO.
In RT mode, the Bus A Word register holds the last valid
MIL-STD-1553 word received on Bus A. The Bus B Word
register holds the last valid MIL-STD-1553 word received on
Bus B.
CLKSEL equals “0” selects a 24 MHz clock while
Each data word for transmit must be written
The FIFO is cleared by Master Reset, at