hx6228 Mospec Semiconductor Corp., hx6228 Datasheet
hx6228
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hx6228 Summary of contents
Page 1
... Typical Operating Power <25 mW/MHz cm -2 • Asynchronous Operation • CMOS or TTL Compatible I/O • Single 5 V ± 10% Power Supply 12 rad(Si)/s • Packaging Options - 32-Lead Flat Pack (0.820 in. x 0.600 in.) - 40-Lead Flat Pack (0.775 in. x 0.710 in.) HX6228 ...
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... HX6228 FUNCTIONAL DIAGRAM A:3-7,12,14- NCS NWE NOE A:0-2, 8-11 SIGNAL DEFINITIONS A: 0-16 Address input pins which select a particular eight-bit word within the memory array. DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write operation. NCS Not chip select, when at a low level allows normal operation. When at a high level NCS forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except CE ...
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... N/cm 9 rad(Si))/s for 32-lead flat pack. Stiffening capacitance is suggested for optimum expected 3 HX6228 Test Conditions ) T =25° Pulse width ≤1 µs Pulse width ≤50 ns, X-ray, VDD=6 =25° =125°C, Adams 90% A worst case environment ...
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... HX6228 ABSOLUTE MAXIMUM RATINGS (1) Symbol Parameter VDD Supply Voltage Range (2) VPIN Voltage on Any Pin (2) TSTORE Storage Temperature (Zero Bias) TSOLDER Soldering Temperature (5 Seconds) PD Maximum Power Power Dissipation (3) IOUT DC or Average Output Current VPROT ESD Input Protection Voltage (4) Θ JC Thermal Resistance (Jct-to-Case) ...
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... V -0.1 DD 2.9 V Valid high + output Vref1 - 249 Vref2 + Valid low - output C L >50 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ 5 HX6228 (2) Units Test Conditions Max VIH=VDD, IO=0, 2.0 mA VIL=VSS, f=0MHz NCS=VDD, IO=0, 2.0 mA f=40 MHz, f=1 MHz, IO=0, CE=VIH=VDD 6.0 mA NCS=VIL=VSS (3) f=1 MHz, IO=0, CE=VIH=VDD 4.5 mA NCS=VIL=VSS (3) +5 µA VSS≤VI≤VDD VSS≤ ...
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... HX6228 READ CYCLE AC TIMING CHARACTERISTICS (1) Symbol Parameter TAVAVR Address Read Cycle Time TAVQV Address Access Time TAXQX Address Change to Output Invalid Time TSLQV Chip Select Access Time TSLQX Chip Select Output Enable Time TSHQZ Chip Select Output Disable Time TEHQV Chip Enable Access Time ...
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... IMPEDANCE DATA IN NCS CE Typical ( AVAVW T AVWH T WLWH T WLQZ T DVWH DATA VALID T SLWH T EHWH 7 HX6228 Worst Case (3) ° -55 to 125 C Units Min Max ...
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... HX6228 DYNAMIC ELECTRICAL CHARACTERISTICS Read Cycle The RAM is asynchronous in operation, allowing the read cycle to be controlled by address, chip select (NCS), or chip enable (CE) (refer to Read Cycle timing diagram). To perform a valid read operation, both chip select and output enable (NOE) must be low and chip enable and write enable (NWE) must be high ...
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... Groups B & D testing as outlined in MIL-STD-883, TM 5005, Class S. The product is quali- fied by following a screening and testing flow to meet the customer’s requirements. Quality conformance testing is performed as an option on all production lots to ensure the ongoing reliability of the product. 9 HX6228 VDD/2 VDD/2 VDD-0.4V High Z 0.4 V ...
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... HX6228 PACKAGING The 128K x 8 SOI SRAM is offered in a custom 32-lead or 40-lead Flat Pack. The package is constructed of multilayer ceramic ( and features internal power and ground 2 3 planes. Ceramic chip capacitors can be mounted to the package by the user to maximize supply noise decoupling and increase ...
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... Top View Kovar Lid [ (Pedestal) Non-Conductive Tie-Bar Bottom View HX6228 S b (width) e (pitch) All dimensions are in inches A 0.131 ± .015 b 0.008 ± 0.002 c 0.006 ± 0.0015 D 0.710 ±0.010 E 0.775 ± 0.007 e 0.025 ± 0.004 F 0.475 ± 0.005 G 0.760 ± ...
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... HX6228 DYNAMIC BURN-IN DIAGRAM* 1 VDD NC 2 A15 A16 F17 R 3 A14 CE F16 R 4 A12 NWE A13 A11 NOE A10 NCS F13 R 12 DQ7 A0 F14 R 13 DQ6 DQ0 ...