adsst-sharc-melody-ultra Analog Devices, Inc., adsst-sharc-melody-ultra Datasheet - Page 7

• Manufacturer Part Number: adsst-sharc-melody-ultra
• Description: Sharc Melody Ultra Audio Processor
• Manufacturer: Analog Devices, Inc.

Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the SHARC Melody Ultra’s
enhanced Harvard architecture, enable unconstrained data flow
between computation units and internal memory. The registers
in PEX are referred to as R0–R15, and in PEY as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The SHARC Melody Ultra features an enhanced Harvard archi-
tecture in which the data memory (DM) bus transfers data and
the program memory (PM) bus transfers both instructions and
data (see F
program and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and an instruction (from the cache), all within a
single cycle.
igure 4
). With the SHARC Melody Ultra’s separate
(HOST OR SLAVE)
COMPATIBLE
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
DEVICE
(OPTIONAL)
(OPTIONAL)
(OPTIONAL)
DEVICES
CLOCK
(2 MAX)
SERIAL
DEVICE
DEVICE
SPI
SERIAL
DEVICE
SERIAL
DEVICE
SERIAL
LINK
12
3
2
MELODY ULTRA
CLKIN
XTAL
CLK_CFG1–0
CLKDBL
EBOOT
LBOOT
IRQ2-0
FLAG11–0
TIMEXP
RPBA
ID2-0
LXCLK
LXACK
LXDAT7–0
SCLK0
FS0
D0A
D0B
SCLK1
FS1
D1A
D1B
SCLK2
FS2
D2A
D2B
SCLK3
FS3
D3A
D3B
SPICLK
SPIDS
MOSI
MISO
RESET
ADSST SHARC
RSTOUT
DATA47–16
ADDR23–0
SDCLK1–0
DMAR1–2
DMAG1–2
CLKOUT
SDCKE
MS3–0
SDA10
BR1–6
SDWE
REDY
BRST
SBTS
JTAG
Figure 4. System Block Diagram
DQM
BMS
ACK
HBR
HBG
RAS
CAS
WR
RD
PA
CS
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Instruction Cache
The SHARC Melody Ultra includes an on-chip instruction
cache that enables 3-bus operation for fetching an instruction
and four data values. The cache is selective—only the instruc-
tions whose fetches conflict with PM bus data accesses are
cached. This cache enables full speed execution of core, looped
operations such as digital filter multiply-accumulates and FFT
butterfly processing.
Data Address Generators with Hardware Circular Buffers
The SHARC Melody Ultra processor’s two data address genera-
tors (DAGs) are used for indirect addressing and implementing
circular data buffers in hardware. Circular buffers enable effi-
cient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
SHARC Melody Ultra contain sufficient registers to enable the
creation of up to 32 circular buffers (16 primary register sets,
16 secondary). The DAGs automatically handle address pointer
CS
DATA
ADDR
DATA
OE
WE
ACK
CS
DATA
DATA
ADDR
ADDR
PERIPHERALS
(OPTIONAL)
PROCESSOR
DMA DEVICE
(OPTIONAL)
(OPTIONAL)
INTERFACE
(OPTIONAL)
MEMORY
ADSST-SHARC-Melody-Ultra
EPROM
AND
HOST
BOOT
RAS
CAS
DQM
CLK
CKE
CS
ADDR
DATA
WE
A10
(OPTIONAL)
SDRAM