adsst-sharc-melody-ultra Analog Devices, Inc., adsst-sharc-melody-ultra Datasheet - Page 16

• Manufacturer Part Number: adsst-sharc-melody-ultra
• Description: Sharc Melody Ultra Audio Processor
• Manufacturer: Analog Devices, Inc.

ADSST-SHARC-Melody-Ultra
Mnemonic
DMAG1
DMAG2
DMAR1
DMAR2
DQM
DxA
DxB
EBOOT
EMU
FLAG11–0
FSx
GND
HBG
HBR
ID2–0
IRQ2–0
LBOOT
LxACK
LxCLK
Type
O/T
O/T
I/A
I/A
O/T
I/O
I/O
I
(O/D)
I/O/A
I/O
G
I/O
I/A
I
I/A
I
I/O
I/O
Function
DMA Grant 1 (DMA Channel 11). Asserted by SHARC Melody Ultra to indicate that the requested DMA starts
on the next cycle. Driven by bus master only. DMAG1 has a 20 kΩ internal pull-up resistor that is enabled for
DSPs with ID2–0 = 00x.
DMA Grant 2 (DMA Channel 12). Asserted by the SHARC Melody Ultra to indicate that the requested DMA
starts on the next cycle. Driven by the bus master only. DMAG2 has a 20 kΩ internal pull-up resistor that is
enabled for DSPs with ID2–0 = 00x.
DMA Request 1 (DMA Channel 11). Asserted by external port devices to request DMA services. DMAR1 has a
20 kΩ internal pull-up resistor that is enabled for DSPs with ID2–0 = 00x.
DMA Request 2 (DMA Channel 12). Asserted by external port devices to request DMA services. DMAR2 has a
20 kΩ internal pull-up resistor that is enabled for DSPs with ID2–0 = 00x.
SDRAM Data Mask. In write mode, DQM has a latency of zero and is used during a precharge command and
during SDRAM power-up initialization.
Data Transmit or Receive Channel A (Serial Ports 0, 1, 2, 3). Each DxA pin has an internal pull-up resistor.
Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to
receive serial data.
Data Transmit or Receive Channel B (Serial Ports 0, 1, 2, 3). Each DxB pin has an internal pull-up resistor.
Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to
receive serial data.
EPROM Boot Select. For a description of how this pin operates, see
system configuration selection that should be hardwired.
Emulation Status. Must be connected to the SHARC Melody Ultra Analog Devices’ DSP Tools product line of
JTAG emulators target board connector only. EMU has an internal pull-up resistor.
Flag Pins. Each pin is configured via control bits as either an input or output. As an input, it can be tested as a
condition. As an output, it can be used to signal external peripherals.
Transmit or Receive Frame Sync (Serial Ports 0, 1, 2, 3). The frame sync pulse initiates shifting of serial data.
This signal is either generated internally or externally. It can be active high or low or an early or late frame
sync, in reference to the shifting of serial data.
Power Supply Return (26 pins).
Host Bus Grant. Acknowledges an HBR bus request, indicating that the host processor may take control of
the external bus. HBG is asserted (held low) by the SHARC Melody Ultra until HBR is released. In a
multiprocessing system, HBG is output by the SHARC Melody Ultra bus master and is monitored by all others.
After HBR is asserted, and before HBG is given, HBG will float for 1 t
grants, HBG should be pulled up with a 20 kΩ to 50 kΩ external resistor.
Host Bus Request. Must be asserted by a host processor to request control of the SHARC Melody Ultra
processor’s external bus. When HBR is asserted in a multiprocessing system, the SHARC Melody Ultra that is
bus master will relinquish the bus and assert HBG. To relinquish the bus, the SHARC Melody Ultra places the
address, data, select, and strobe lines in a high impedance state. HBR has priority over all SHARC Melody Ultra
bus requests (BR6–1) in a multiprocessing system.
Multiprocessing ID. Determines which multiprocessing bus request (BR6–1) is used by the SHARC Melody
Ultra. ID = 001 corresponds to BR1, ID = 010 corresponds to BR2, and so on. Use ID = 000 or ID = 001 in single-
processor systems. These lines are a system configuration selection that should be hardwired or only
changed at reset.
Interrupt Request Lines. These pins are sampled on the rising edge of CLKIN and may be either edge-
triggered or level-sensitive.
Link Boot. For a description of how this pin operates, see
configuration selection that should be hardwired.
Link Port Acknowledge (Link Ports 0–1). Each LxACK pin has an internal pull-down 50 kΩ resistor that is
enabled or disabled by the LxPDRDE bit of the LCTL register.
Link Port Clock (Link Ports 0–1). Each LxCLK pin has an internal pull-down 50 kΩ resistor that is enabled or
disabled by the LxPDRDE bit of the LCTL register.
Rev. 0 | Page 16 of 28
Table 3
on page 18. This signal is a system
CK
Table 3
(1 CLKIN cycle). To avoid erroneous
on page 18. This signal is a