gs820e32a GSI Technology, gs820e32a Datasheet - Page 8

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gs820e32a

Manufacturer Part Number
gs820e32a
Description
2mb Synchronous Burst Sram
Manufacturer
GSI Technology
Datasheet
Notes:
1.
2.
3.
Rev: 1.08 1/2009
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.
The upper portion of the diagram assumes active use of only the Enable (E
inputs, and that ADSP is tied high and ADSC is tied low.
The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and
assumes ADSP is tied high and ADV is tied low.
X
CW
X
First Write
Burst Write
W
W
Simplified State Diagram
CW
8/20
W
CR
R
CR
R
Deselect
X
1,
E
2,
E
3
R
) and Write (B
CR
First Read
Burst Read
R
R
GS820E32AT-180/166/133/4/5
A
, B
B
CR
, B
X
C
X
, B
D
, BW, and GW) control
© 2000, GSI Technology

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