gs8662dt10bgd-450i GSI Technology, gs8662dt10bgd-450i Datasheet - Page 8

• Manufacturer Part Number: gs8662dt10bgd-450i
• Description: 72mb Sigmaquad-ii+tm Burst Of 4 Sram
• Manufacturer: GSI Technology

Resulting Write Operation
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad-II+ SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to
V
5X the value of the desired RAM output impedance. The allowable range of RQ to guarantee impedance matching continuously is
between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts
in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance
evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is
implemented with discrete binary weighted impedance steps.
Input Termination Impedance Control
These SigmaQuad-II+ SRAMs are supplied with programmable input termination on Data (D), Byte Write (BW), and Clock (K,K)
input receivers. The input termination is always enabled, and the impedance is programmed via the same RQ resistor (connected
between the ZQ pin and V
is tied Low, input termination is "strong" (i.e., low impedance), and is nominally equal to RQ*0.3 Thevenin-equivalent when RQ is
between 175Ω and 350Ω. When the ODT pin is tied High (or left floating—the pin has a small pull-up resistor), input termination
is "weak" (i.e., high impedance), and is nominally equal to RQ*0.6 Thevenin-equivalent when RQ is between 175Ω and 250Ω.
Periodic readjustment of the termination impedance occurs to compensate for drifts in supply voltage and temperature, in the same
manner as for driver impedance (see above).
Note:
D, BW, K, K inputs should always be driven High or Low; they should never be tri-stated (i.e., in a High-Z state). If the inputs are
tri-stated, the input termination will pull the signal to V
the receiver to enter a meta-stable state, resulting in the receiver consuming more power than it normally would. This could result
in the device’s operating currents being higher.
Rev: 1.00 5/2011
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
SS
via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
Byte 1
D0–D8
Written
Beat 1
Unchanged
D9–D17
Byte 2
SS
) used to program output driver impedance, in conjuction with the ODT pin (6R). When the ODT pin
Unchanged
Byte 1
D0–D8
Beat 2
D9–D17
Byte 2
Written
DDQ
8/29
/2 (i.e., to the switch point of the diff-amp receiver), which could cause
GS8662DT07/10/19/37BD-450/400/350/333/300
Byte 1
D0–D8
Written
Beat 3
D9–D17
Byte 2
Written
Unchanged
Byte 1
D0–D8
© 2011, GSI Technology
Beat 4
D9–D17
Byte 2
Written